Interrupts Generated By On-Chip Modules; Timers - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

Interrupts Generated by On-Chip Modules

A level-sensitive interrupt is normally driven as a result of some accessible
register state and cleared either by reading the register or by writing an
inactive value into it.
An edge-sensitive interrupt is event triggered (for example, by a timer).
Interrupts Generated by On-Chip
Modules
Interrupts generated by on-chip modules differ depending on the specific
TigerSHARC processor configuration.

Timers

The vector registers are:
•
IVTIMER0HP
•
IVTIMER1HP
•
IVTIMER0LP
•
IVTIMER1LP
After reset, the timer interrupts are disabled and vectors are not initialized.
There are four timer interrupts: two for each timer, one as high priority
and one as low priority. When the timer interrupt occurs, both high and
low priority bits are set in
Bit52). The purpose of having the two priorities per timer is to enable the
user to choose which priority is needed. This is accomplished by enabling
the appropriate interrupt. Only one bit is cleared when the interrupt rou-
tine is served. If both high and low priority interrupts are enabled, the
interrupt is serviced twice. The assumption is that only one of the inter-
rupts is enabled.
4-4
– interrupt priority 52; edge-triggered
– interrupt priority 53; edge-triggered
– interrupt priority 2; edge-triggered
– interrupt priority 3; edge-triggered
(for example, for Timer 0 both Bit2 and
ILAT
ADSP-TS101 TigerSHARC Processor
Hardware Reference