Setting The Sdram Power-Up Mode (Init Sequence) - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

Setting the SDRAM Power-Up Mode (Init Sequence)

To avoid unpredictable start-up modes, SDRAM devices must follow a
specific initialization sequence during power-up. The processor provides
two commonly used power-up options.
The Init Sequence bit (14) in the
power-up mode. When set (=1), the SDRAM controller sequentially
issues: a command, eight AutoRefresh cycles, and an
PRE
ister Set) command. When cleared (=0), the SDRAM controller issues, in
this order: a
PRE
eight AutoRefresh cycles.
SDRAM Interface Throughput
Table 6-10 lists the data throughput rates for the processor's core or DMA
read/write accesses to SDRAM. The following assumptions are made for
the information in this table:
latency = 2 cycles (CL = 2)
CAS
No SDRAM buffering (pipeline depth = 0)
Precharge (t ) = 2 cycles
RP
Active command time (t
t (fixed) =
CL
RCD
Table 6-10. Data Throughput Rates
Accesses
Sequential Uninterrupted
Non-sequential Uninterrupted Read
ADSP-TS101 TigerSHARC Processor
Hardware Reference
SDRCON
command, an
MRS
) = 3 cycles
RAS
= 2 cycles
Operations
Read
register selects the SDRAM
(Mode Register Set) command, and
1,2
Page Throughput per SDRAM Clock
(64-bit words)
Same 1 word/1 cycle
Same 1 word/1 cycle
SDRAM Interface
(Mode Reg-
MRS
6-27