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01 = 2 cycles latency
10 = 3 cycles latency
11 = Reserved
Generally, the frequency of the operation determines the value of the
latency.
Setting the SDRAM Buffering Option (Pipeline
depth)
Systems that use several SDRAM devices connected in parallel may
require buffering between the processor and multiple SDRAM devices in
order to meet overall system timing requirements. To meet such timing
requirements and enable intermediary buffering, the processor supports
pipelining of SDRAM address and control signals. The pipeline depth
Bit3 in the
SDRCON
Pipeline depth = 0 Disable pipelining
Pipeline depth = 1 Enable pipelining
When set (= 1), the SDRAM controller delays the data in write accesses by
one cycle, enabling the processor to latch the address and controls exter-
nally. In read accesses, the SDRAM controller samples data one cycle
later.
Figure 6-6 on page 6-24 shows another single processor example in which
the SDRAM interface connects to multiple banks of SDRAM to provide
512M of SDRAM in a 4-bit I/O configuration. This configuration results
in 16M x 32-bit words. In this example, 0xA and 0xB output from the
registered buffers are the same signal, but are buffered separately. In the
registered buffers, a delay of one clock cycle occurs between the input (Ix)
and its corresponding output (0xA or 0xB).
ADSP-TS101 TigerSHARC Processor
Hardware Reference
register enables this mode:
SDRAM Interface
CAS
6-23
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