Interrupt Pins (Irq) - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

Interrupts Generated by On-Chip Modules
•
IVDMA9
•
IVDMA10
•
IVDMA11
•
IVDMA12
•
IVDMA13
After reset, the DMA interrupts are enabled and vectors are initialized to
zero for boot purposes.
There are 14 DMA channels, each of which can generate an interrupt. If
the interrupt bit in its
channel completes its block.

Interrupt Pins (IRQ)

The vector registers are:
•
IVIRQ0
ble, init value: 0x10000000
•
IVIRQ1
ble, init value: 0x08000000
•
IVIRQ2
ble, init value: 0x0C000000
•
IVIRQ3
ble, init value: 0x0
The interrupt type is edge- or level-triggered according to SQCTL pro-
gramming. See "Sequencer Control Register – SQCTL" on page 2-16.
After reset, the
pin ) is used. Vectors are initialized for boot purposes.
BM
4-6
– interrupt priority 30; edge-triggered
– interrupt priority 31; edge-triggered
– interrupt priority 32; edge-triggered
– interrupt priority 37; edge-triggered
– interrupt priority 38; edge-triggered
is set, an interrupt is set when the appropriate
TCB
– interrupt priority 41, edge-/level-triggered, programma-
– interrupt priority 42, edge-/level-triggered, programma-
– interrupt priority 43, edge-/level-triggered, programma-
– interrupt priority 44, edge-/level-triggered, programma-
interrupts are disabled, unless
IRQ IRQEN
ADSP-TS101 TigerSHARC Processor
Hardware Reference
strap option (on