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Table 10-2. General Pin Descriptions
Signal
ACK
ADDR31–0
BM
BMS
BOFF
BR7–0
BRST
BUSLOCK
CAS
CONTROLIMP2–1
CONTROLIMP0
CPA
DATA63–0
DMAR3–0
DPA
DS2–0
EMU
FLAG3–0
FLYBY
HBG
HBR
HDQM
ID2–0
ADSP-TS101 TigerSHARC Processor
Hardware Reference
Type
Description
I/O/T
Acknowledge
I/O/T
Address Bus
O
Bus Master
O/T
Boot Memory Select
I/O/T
Back Off
I/O
Multiprocessing Bus Request Pins
I/O/T
Burst
O/T
Bus Lock Indication
I/O/T
Column Address Select
I
Impedance Control
I
Impedance Control
I/O (o/d) Core Priority Access
I/O/T
External Data Bus
I/A
DMA Request Pins
I/A
DMA Request Pins
I
Digital Drive Strength Selection
O (o/d)
Emulation
I/O/A
FLAG pins
O/T
Flyby Mode
I/O/T
Host Bus Grant
I
Host Bus Request
O/T
High Word SDRAM Data Mask
I
Multiprocessor ID
System Design
10-5
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