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DMA Control and Status Registers
The
and
DSTAT
quad-word. Normal word reading of these registers is not permitted.
Figure 7-10. DSTAT (Bits 63-48) Register Bit Descriptions
Bits17-15 continued on Figure 7-13
Figure 7-11. DSTAT (Bits 31-16) Register Bit Descriptions
7-24
registers must be read as either a long or
DSTATC
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved
CH13
CH12
Reserved
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved
CH7
CH6
CH5
ADSP-TS101 TigerSHARC Processor
Hardware Reference
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