Hardware Error Operations - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

Interrupts Generated by On-Chip Modules

Hardware Error Operations

Hardware errors generate actions defined by the vector register as follows.
• – interrupt priority 57, level-triggered, active as long as any of
IVHW
the status registers set by events in the list below indicate an error
(by issuing an
• Error in DMA – one of the
initialization error). Refer to "DMA Status Register
(DSTAT/DSTATC)" on page 7-23.
• Data written to the AutoDMA while the corresponding AutoDMA
channel is not initialized. Active while Bit17 of
Refer to the register description for "SYSTAT/SYSTATCL Regis-
ter" on page 2-31.
• Broadcast read from external. Active while Bit16 of
active. Refer to the register description for "SYSTAT/SYSTATCL
Register" on page 2-31.
• Access to SDRAM when it is not enabled. Active while Bit18 of
SYSTAT
TAT/SYSTATCL Register" on page 2-31.
• Self multiprocessing read – active when Bit19 of
Refer to the register description for "SYSTAT/SYSTATCL Regis-
ter" on page 2-31.
• Link error – in one of the
indicate an error. Refer to "Error Detection Mechanisms" on
page 8-17.
For additional information refer to "Status Register (LSTATx)" on
page 8-23).
After reset, the hardware error interrupt is disabled and vectors are not
initialized.
4-8
interrupt).
HWILL
is active. Refer to the register description for "SYS-
fields in
CHxx DSTAT
registers in the fields
LSTATx
ADSP-TS101 TigerSHARC Processor
register is 100 (
TCB
is active.
SYSTAT
is
SYSTAT
is active.
SYSTAT
or
RER TER
Hardware Reference