Bus Width - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

SYSCON Programming

Bus Width

The bus width is configured separately for memory access, host transac-
tions (either as master or as slave), and multiprocessing. The setup is zero
for a 32-bit bus and one for a 64-bit bus. Note that if either the host or
memory bus width is 64-bits, the multiprocessing width must also be
64-bits. The valid width settings are shown in Table 5-2.
Table 5-2. Valid Width Settings
000 allowed
001 not allowed
010 allowed
011 allowed
100 not allowed
101 not allowed
110 allowed
111 allowed
Slow Device Protocol
For slow device protocol setup, the slow protocol bit (Bit5 for bank 0,
Bit11 for bank 1, and Bit17 for host) is set. Additionally, the pipeline
depth field is set to
programmed either way. The internal wait field identifies the number of
internal wait cycles on slow accesses. If the number of internal waits is
zero, the external wait mechanism cannot be used for these transactions.
5-14
and the
0b00 IDLE
ADSP-TS101 TigerSHARC Processor
bit is a "don't care" bit—it can be
Hardware Reference