Dcntst Register - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

DMA Control and Status Registers

DCNTST Register

is a 32-bit register alias used to set
DCNTST
is ORed with
DCNTST
ple, writing a 1 to bit n in the register sets the corresponding bit n in the
register.
DCNT
DCNTCL Register
is a 32-bit register alias used to clear
DCNTCL
to is ANDed with
DCNTCL
example, writing a 0 to bit n in the register resets the corresponding bit n
in the register.
DCNT
DMA Control Register Restrictions
The following restrictions apply to the DMA Control registers.
Operand Length Setup (Len)
In external port (EP) channels, the
quad-word) must be the same in both
or destination
word).
In link (receive and transmit) channels the
quad-word (0x3). For AutoDMA channels, the
as the transactions to the AutoDMA register.
Count (XCOUNT and YCOUNT)
For EP channels, the total counts should be identical.
•
DX_COUNT
•
DX_COUNT * DY_COUNT
7-28
, and the result is loaded into
DCNT
, and the result is loaded into
DCNT
is boot EPROM, the
TCB
: when the
2DDMA
: when the
bits. The value written to
DCNT
bits. The value written
DCNT
field (normal word, long-word or
LEN
s. If the
TCB TY
field must be 0x1 (normal
LEN
field must always be
LEN
field must be the same
LEN
bit is cleared
bit is set
2DDMA
ADSP-TS101 TigerSHARC Processor
. For exam-
DCNT
. For
DCNT
setup of either source
Hardware Reference