Internal Memory Tcb - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

Internal Memory TCB

Upon reset, the DMA initiates a transfer by requesting external data from
OFIFO:
• The TigerSHARC processor reads the data from boot EPROM
into its IFIFO.
• The IFIFO gets the return address from receiver
initiates an internal write access.
• After transferring the complete block, the DMA interrupts the core
and jumps it to address 0x00000000.
Table 10-6. EPROM Boot – Internal Memory TCB
Receiver TCB Configuration
Register Field
DI
DX
DY
DP TY
DP PR
DP 2DDMA
DP LEN
DP INT
DP DRQ
DP CHEN
DP CHTG
DP CHPT
ADSP-TS101 TigerSHARC Processor
Hardware Reference
Description
0x00000000
Number of words to transfer is 256.
Address modifier is set to 0x0001.
0x0000
Internal memory
1
0
Word
1
0
0
0x0
0x00000
System Design
register and
TCB
10-35