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6 SDRAM INTERFACE
The TigerSHARC processor has a dedicated address space to support
SDRAM. This address space is selected by the
SDRAM), which can be used for direct interface with SDRAM devices.
The SDRAM is accessed on memory address range 0x04000000 to
0x07FFFFFF (see "External Memory Bank Space" on page 2-4).
SDRAM, unlike conventional DRAM, is synchronous to the SCLK (sys-
tem clock). All inputs are sampled and all outputs are valid at the rising
edge of the clock. The synchronous interface allows data transfer every
cycle, yielding high throughput up to 400M Bytes/second for a 32-bit bus
width, and 800M Bytes/second for a 64-bit bus width. The SDRAM has
several types of burst accesses, depending on the initialization of its mode
register,
SDRCON
ate command to the SDRAM. The SDRAM specific modes should be
initialized in the
tion) (DMA 0x180484)" on page 2-36.) The SDRAM interface provides a
glueless interface with standard SDRAMs—6M bits, 64M bits, 128M
bits, 256M bits, and 512M bits. The TigerSHARC processor directly sup-
ports a maximum of 64M words x 32 bits of SDRAM.
For SDRAM, all initialization
configuration is done by processor with ID000. This ID should always be
present in any TigerSHARC processor cluster.
ADSP-TS101 TigerSHARC Processor
Hardware Reference
. Each access type is preceded by issuance of the appropri-
register. (See "SDRCON (SDRAM Configura-
SDRCON
MRS
(Memory Select
MSSD
(Mode Register Set) command and
6-1
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