Backoff - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

Multiprocessing
• If the host uses SDRAM, the TigerSHARC processor should not
use SDRAM before the TigerSHARC processor (ID #0) has initial-
ized the SDRAM. (see "SDRAM Programming" on page 6-19).
• If the host uses SDRAM, it puts the SDRAM in self-refresh mode
before it relinquishes the bus to the host. The host, in order to use
the SDRAM, should change the SDRAM mode to normal work.
Before returning the bus to the TigerSHARC processor, the host
should put the SDRAM into self-refresh mode again.
When the host executes burst transactions to and from the TigerSHARC
processor, the TigerSHARC processor allows for a continuous burst of
more than four data units. The host issues a starting burst address. As long
as is asserted, the TigerSHARC processor increments the address
BRST
internally. The
this case the transaction is ended on every quad-word address. The first
transaction should begin and the last transaction should end in quad-word
aligned addresses.

Backoff

The host, one of the masters in the system, can request the bus, as
explained in "Bus Arbitration Protocol" on page 5-41. In some cases, a
deadlock situation may occur. This happens when the host and the Tiger-
SHARC processor are trying to read from each other's bus at the same
time—see Figure 5-24 on page 5-52. In this case, the TigerSHARC pro-
cessor has control of its system bus, the host has control of its system bus,
and both issue a read transaction from each other. This results in the host
bridge requesting both buses to execute both transactions. Neither of the
buses is relinquished before the current master completes its own transac-
tion. Likewise, neither of the transactions is completed because the buses
are not relinquished. To resolve the deadlock, one of the requesters has to
give up the bus, allowing the other requester to complete its read transac-
tion. The TigerSHARC processor is designed to yield the bus to the host
when the latter asserts
5-50
pin is used to indicate transaction continuation—in
BRST
, signaling the TigerSHARC processor to yield.
BOFF
ADSP-TS101 TigerSHARC Processor
Hardware Reference