Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual page 394

INDEX
DMA Channel Prioritization 7-36
DMA Channel Priority 7-36
DMA Channel Priority 7-38
DMA Channels 7-34
DMA Control and Status Register
2-46
DMA Control and Status Register
2-46
DMA Control and Status Registers
7-23
DMA Control Register Restric-
tions 7-28
DMA Control Registers 7-26
DMA Controller 1-22
DMA Controller Features 7-7
DMA Controller Operations 7-32
DMA Data Register Boot
Internal Memory TCB 10-37
DMA Interrupts 4-5, 7-48
DMA Memory Accesses 7-34
DMA Operation on Boot 10-32
DMA Priority Access (DPA) 5-39,
5-41, 5-43, 5-43–5-46
DMA Priority Access DPA 5-43
DMA Registers 2-41
DMA Request 7-30
DMA Request (DMAR) 1-22, 7-8,
7-12, 7-12–7-13, 7-32, 7-61, 7-62,
8-6
DMA Semaphores 7-59
DMA Status Register (DSTAT)
7-23
DMA Throughput 7-66
DMA Transfer Control Block Reg-
vi
isters 7-15
DMA Transfers 7-33
DMAR I/O Pins 7-12
DPx Register 7-18
DPx Register Bit Descriptions
7-20
DSP Architecture 1-6
DSP architecture 1-6
DSP Product Information -xxiii
DSP product information -xxiii
Dual TCB Channel 7-52, 7-53
DXx Register 7-17
DYx Register 7-17
E
edge sensitive 3-6, 3-8, 4-3–4-4,
4-7, 4-16, 10-8
EMU 9-13
emulation 1-19
EMU 9-13
EMUIR register 4-23
emulation debug 4-15
emulation exception 3-3, 4-16,
4-23
emulation instruction 3-3
emulation interrupt 4-3
emulation trap 3-3, 4-10, 4-25,
9-8
Emulation and Test Support 1-24
Emulation Debug 4-10
emulation debug 4-10
Emulation Mode 3-3
emulation mode 3-1, 3-2, 3-3–3-4,
4-10, 4-16, 9-2
ADSP-TS101 TigerSHARC Processor
Hardware Reference