Link Architecture - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

Link Architecture

Link Architecture
The link port has two parts—transmitter and receiver. Each has a shift
register and buffer, as shown in Figure 8-1 on page 8-2. The
registers are memory-mapped Uregs. The shift registers are not
LBUFRx
accessible by software. All are 128-bit registers.
Figure 8-1. Link Port Architecture
Link I/O Pins
Table 8-1 describes the I/O pins related to the link ports. There is a set of
link pins for each link port. The 'x' in the signal name indicates the link
port—0, 1, 2, or 3.
8-2
INTERNAL BUS
TX TRANSMITTER RX RECEIVER
BUFFER
TRANSMITTER
SHIFT REGISTER
LINK PORT
ADSP-TS101 TigerSHARC Processor
BUFFER
RECEIVER
SHIFT REGISTER
Hardware Reference
and
LBUFTx