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Transactions can be initiated on the external bus and driven into internal
TigerSHARC processor elements. For example, memory and Uregs can be
read and written by an external bus master—another TigerSHARC pro-
cessor or host. The transaction is identified according to the memory map
(see "Multiprocessor Space" on page 2-5) and processor ID, strobed by the
IFIFO, and driven on the internal bus in turn. If the external transaction
is read, the data is returned to the master that initiated the transaction
through the slave's OBUF.
On DMA transactions (reads or writes), addresses are written to the
OFIFO through the I/O address bus and not the internal address bus in
order to reduce internal bus activity. Only the data read from the external
bus is transferred on an internal bus.
The internal buses are used for both external and internal transactions,
where each bus can execute a new transaction every cycle. The cause of a
transaction can be instruction fetch, DMA transfer, Load or Store instruc-
tion or IFIFO (internal address accessed by an external master or data
returned from an external read).
The bus selection for the execution of a particular transaction is per-
formed according to memory address. If internal memory is involved in
the transaction, the selected bus is the bus of that memory. (For example,
if the access is targeted to memory block 0, the transaction is executed on
bus #0.)
When a transaction occurs between registers or between external memory
and a register, it can be executed on any internal bus. This type of transac-
tion, called a "virtual bus transaction", is executed on the first available
internal bus. If no bus becomes available for four cycles, one of the three
internal buses is forced to service the virtual bus transaction. Even when
more than one bus is not assigned to regular bus transactions, only one
virtual bus transaction can be executed in a given cycle.
ADSP-TS101 TigerSHARC Processor
Hardware Reference
Cluster Bus
5-9
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