Dma/Memory Dma Control Registers - Analog Devices ADSP-BF506F Hardware Reference Manual

Table A-4. System Reset and Interrupt Control Registers (Cont'd)
Memory-Mapped
Address
0xFFC0 0124
0xFFC0 0164

DMA/Memory DMA Control Registers

DMA control registers (0xFFC0 0B00 – 0xFFC0 0FFF) are listed in
Table A-5.
Table A-5. DMA Traffic Control Registers
Memory-Mapped
Address
0xFFC0 0B0C
0xFFC0 0B10
Since each DMA channel has an identical MMR set, with fixed offsets
from the base address associated with that DMA channel, it is convenient
to view the MMR information as provided in
Table A-6 identifies the base address of each DMA channel, as well as the
register prefix that identifies the channel.
suffix and provides its offset from the Base Address.
As an example, the DMA channel 0 Y_MODIFY register is called
, and its address is 0xFFC0 0C1C. Likewise, the memory DMA
MODIFY
stream 0 source current address register is called
its address is 0xFFC0 0E64.
ADSP-BF50x Blackfin Processor Hardware Reference
Register
Name
SIC_IWR0
SIC_IWR1
Register Name
DMA_TC_PER
DMA_TC_CNT
System MMR Assignments
For individual bits, see this diagram:
"System Interrupt Wakeup-Enable (SIC_IWR)
Register" on page 4-12
"System Interrupt Wakeup-Enable (SIC_IWR)
Register" on page 4-12
For individual bits, see this diagram:
"DMA_TC_PER Register" on page 7-90
"DMA_TC_CNT Register" on page 7-90
Table A-6
Table A-7 then lists the register
MDMA_S0_CURR_ADDR
and Table A-7.
DMA0_Y_
, and
A-5