Analog Devices ADSP-BF506F Hardware Reference Manual page 1216

Ports Registers
Table A-8. Ports Registers (Cont'd)
Memory-Mapped
Address
0xFFC0 1700
0xFFC0 1704
0xFFC0 1708
0xFFC0 170C
0xFFC0 1710
0xFFC0 1714
0xFFC0 1718
0xFFC0 171C
0xFFC0 1720
0xFFC0 1724
0xFFC0 1728
0xFFC0 172C
0xFFC0 1730
0xFFC0 1734
0xFFC0 1738
0xFFC0 173C
0xFFC0 1740
0xFFC0 3200
0xFFC0 3204
A-10
Register Name
PORTHIO
PORTHIO_CLEAR
PORTHIO_SET
PORTHIO_TOGGLE
PORTHIO_MASKA
PORTHIO_MASKA_CLEAR
PORTHIO_MASKA_SET
PORTHIO_MASKA_TOGGLE
PORTHIO_MASKB
PORTHIO_MASKB_CLEAR
PORTHIO_MASKB_SET
PORTHIO_MASKB_TOGGLE
PORTHIO_DIR
PORTHIO_POLAR
PORTHIO_EDGE
PORTHIO_BOTH
PORTHIO_INEN
PORTF_FER
PORTG_FER
ADSP-BF50x Blackfin Processor Hardware Reference
For individual bits, see this diagram:
"GPIO Data Registers" on page 9-31
"GPIO Clear Registers" on page 9-32
"GPIO Set Registers" on page 9-32
"GPIO Toggle Registers" on page 9-33
"GPIO Mask Interrupt A Registers" on
page 9-35
"GPIO Mask Interrupt A Clear Registers" on
page 9-38
"GPIO Mask Interrupt A Set Registers" on
page 9-36
"GPIO Mask Interrupt A Toggle Registers" on
page 9-40
"GPIO Mask Interrupt B Registers" on
page 9-35
"GPIO Mask Interrupt B Clear Registers" on
page 9-39
"GPIO Mask Interrupt B Set Registers" on
page 9-37
"GPIO Mask Interrupt B Toggle Registers" on
page 9-41
"GPIO Direction Registers" on page 9-30
"GPIO Polarity Registers" on page 9-33
"Interrupt Sensitivity Registers" on page 9-34
"GPIO Set on Both Edges Registers" on
page 9-34
"GPIO Input Enable Registers" on page 9-31
"Function Enable Registers" on page 9-30
"Function Enable Registers" on page 9-30