Managing Core And System Clocks; Configuring And Servicing Interrupts - Analog Devices ADSP-BF506F Hardware Reference Manual

Configuring and Servicing Interrupts

Managing Core and System Clocks

The processor produces a multiplication of the clock input provided on
the pin to generate the PLL
CLKIN
produce the core clock (
is based on a divider ratio that is programmed via the
the register. The system clock is based on a divider ratio that is
PLL_DIV
programmed via the
information about how to set and change
Chapter 16, "Dynamic Power Management".
Configuring and Servicing Interrupts
A variety of interrupts are available. They include both core and periph-
eral interrupts. The processor assigns default core priorities to system-level
interrupts. However, these system interrupts can be remapped via the sys-
tem interrupt assignment registers (
the System Interrupts chapter.
The processor core supports nested and non-nested interrupts, as well as
self-nested interrupts. For explanations of the various modes of servicing
events, please see Blackfin Processor Programming Reference.
Semaphores
Semaphores provide a mechanism for communication between multiple
processors or processes/threads running in the same system. They are used
to coordinate resource sharing. For instance, if a process is using a particu-
lar resource and another process requires that same resource, it must wait
until the first process signals that it is no longer using the resource. This
signalling is accomplished via semaphores.
25-2
VCO
) and the system clock (
CCLK
bit settings in the
SSEL
SIC_IARx
ADSP-BF50x Blackfin Processor Hardware Reference
clock. This clock is divided to
VCO
). The core clock
SCLK
CSEL
register. For detailed
PLL_DIV
and
CCLK SCLK
). For more information, see
bit settings in
frequencies, see