High-Frequency Design Considerations; Signal Integrity - Analog Devices ADSP-BF506F Hardware Reference Manual

High-Frequency Design Considerations

Because the processor can operate at very fast clock frequencies, signal
integrity and noise problems must be considered for circuit board design
and layout. The following sections discuss these topics and suggest various
techniques to use when designing and debugging signal processing
systems.

Signal Integrity

In addition to reducing signal length and capacitive loading, critical sig-
nals should be treated like transmission lines.
Capacitive loading and signal length of buses can be reduced by using a
buffer for devices that operate with wait states (for example, SDRAMs).
This reduces the capacitance on signals tied to the zero-wait-state devices,
allowing these signals to switch faster and reducing noise-producing cur-
rent spikes. Extra care should be taken with certain signals such as external
memory, read, write, and acknowledge strobes.
Use simple signal integrity methods to prevent transmission line reflec-
tions that may cause extraneous extra clock and sync signals. Additionally,
avoid overshoot and undershoot that can cause long term damage to input
pins.
Some signals are especially critical for short trace length and usually
require series termination. The
ing series resistance at its driver. SPORT interface signals
and should use some termination. Although the serial ports may be
TFS
operated at a slow rate, the output drivers still have fast edge rates and for
longer distances the drivers often require resistive termination located at
the source. (Note also that
multi-channel mode.) On the PPI interface, the
also benefit from these standard signal integrity techniques. If these pins
have multiple sources, it will be difficult to keep the traces short.
ADSP-BF50x Blackfin Processor Hardware Reference
pin should have impedance match-
CLKIN
and should not be shorted in
TFS RFS
System Design
,
TCLK RCLK
and
PPI_CLK SYNC
, ,
RFS
signals
25-5