Uart Slave Mode Boot - Analog Devices ADSP-BF506F Hardware Reference Manual

16-bit DMA X Count limits the maximum width of a pulse to 0xFFFF
words.
After completion of the DMA transfer, the
nated and cleared in the required manner. This mode of operation does
impose some restrictions on the amount of time that the PPI host device
can hold off a transfer. If a DMA transfer consists of 0xFFFF words, the
timer period will be reached 0xFFFF0000
tion of the
PPI_FS2
identical
PPI_FS2
and the
PWM_OUT
In the unlikely event that a user requires a transfer to be held off for this
significant amount of time, the PPI host must be able to ignore any fur-
ther /TMR1 assertions until the currently pending transaction
PPI_FS2
that was delayed has completed. If the master is not capable of ignoring
further
PPI_FS2
completes allowing for the
pletion of the timer pulse period of 0xFFFFFFFF

After PPI boot completion the PPI interface is disabled and the
PPI_CONTROL
not done for the Timer1 registers. Although the timer is disabled,
the
TIMER1_CONFIG
value.

UART Slave Mode Boot

Figure 24-17 shows the interconnection required for booting. The figure
does not show physical line drivers and level shifters that are typically
required to meet the individual UART-compatible standards.
For = 111, the ADSP-BF50x processor consumes boot data from a
BMODE
UART host device connected to the UART0 interface. Automatic control
of the
UA0_RTS
ADSP-BF50x Blackfin Processor Hardware Reference
/TMR1 signal. This will result in the generation of an
/TMR1 pulse if the DMA transfer has not completed
timer has not been disabled.
/TMR1 assertions, the master must ensure that the DMA
PWM_OUT
register is cleared, this register-clearing operation is
register is not reloaded with the default reset
output provides flow control.
System Reset and Booting
out mode is termi-
PWM_OUT
cycles after the deasser-
PPI_CLK
timer to be disabled prior to the com-
PPI_CLK
cycles.
24-55