Analog Devices ADSP-BF506F Hardware Reference Manual page 1212

DMA/Memory DMA Control Registers
Table A-6. DMA Channel Base Addresses
DMA Channel Identifier
0
1
2
3
4
5
6
7
8
9
10
11
MemDMA stream 0 destination
MemDMA stream 0 source
MemDMA stream 1 destination
MemDMA stream 1 source
Table A-7. DMA Register Suffix and Offset
Register Suffix
NEXT_DESC_PTR
START_ADDR
CONFIG
A-6
MMR Base Address
Offset For individual bits, see this diagram:
From Base
0x00 "DMA Next Descriptor Pointer Registers (DMAx_NEXT_
DESC_PTR/ MDMA_yy_NEXT_DESC_PTR)" on
page 7-81
0x04 "DMA Start Address Registers (DMAx_START_
ADDR/MDMA_yy_START_ADDR)" on page 7-75
0x08 "DMA Configuration Registers (DMAx_CONFIG/MDMA_
yy_CONFIG)" on page 7-68
ADSP-BF50x Blackfin Processor Hardware Reference
0xFFC0 0C00
0xFFC0 0C40
0xFFC0 0C80
0xFFC0 0CC0
0xFFC0 0D00
0xFFC0 0D40
0xFFC0 0D80
0xFFC0 0DC0
0xFFC0 0E00
0xFFC0 0E40
0xFFC0 0E80
0xFFC0 0EC0
0xFFC0 0F00
0xFFC0 0F40
0xFFC0 0F80
0xFFC0 0FC0
Register Prefix
DMA0_
DMA1_
DMA2_
DMA3_
DMA4_
DMA5_
DMA6_
DMA7_
DMA8_
DMA9_
DMA10_
DMA11_
MDMA_D0_
MDMA_S0_
MDMA_D1_
MDMA_S1_