Analog Devices ADSP-BF506F Hardware Reference Manual page 1152

Specific Boot Modes
The pull-up resistor on the
detection. The pull-up resistor on the
memory is in a known state when the Blackfin GPIO is in a high-imped-
ance state (for example, during reset). A pull-down resistor on the
line displays cleaner oscilloscope plots during debugging.
For SPI master boot, the
ister. For details see
= 2, the receive DMA mode is selected. Clearing both the
TIMOD
bits results in SPI mode 0. The boot kernel does not allow SPI0
CPHA
hardware to control the
GPIO mode by software. Initialization code is allowed to manipulate the
variable in the
uwSsel
nism to a second SPI memory connected to another GPIO pin.
By default, the boot kernel sets the
resulting in a bit rate of
Table 24-9. Bit Rate
SPI_BAUD
133
Reserved
2
4
8
16
32
64
Similarly, the boot kernel uses the standard 0x03 SPI read command, by
default.
24-48
line is required for automatic device
MISO
,
SPE MSTR
Chapter 18, "SPI-Compatible Port
SPI0_SSEL1
ADI_BOOT_DATA
/266 (as shown in
SCLK
Bit Rate
SCLK/(2x133) << default
SCLK/(2x2)
SCLK/(2x4)
SCLK/(2x8)
SCLK/(2x16)
SCLK/(2x32)
SCLK/(2x64)
ADSP-BF50x Blackfin Processor Hardware Reference
line ensures that the
SPI0_SSEL1
and bits are set in the
SZ
pin. Instead, this pin is toggled in
structure to extend the boot mecha-
register to a value of 133,
SPI0_BAUD
Table
SPI0SCK
reg-
SPI0_CTL
Controller". With
and
CPOL
24-9).