Analog Devices ADSP-BF506F Hardware Reference Manual page 1162

Specific Boot Modes
1
UA0_TX
UA0_RX
UA0_RTS
RESET
HWAIT 0
Figure 24-19. UART Boot - Host Relying on HWAIT
As shown in Figure
encouraging the host to send the boot stream data immediately. With a
half-duplex UART connection this must be avoided. The host should
either rely on the
from the Blackfin processor, before sending any data.
UA0_TX
UA0_RX
UA0_RTS
RESET
HWAIT 0
Figure 24-20. UART Boot - Host Relying on RTS
For UART boot, it is not obvious on how to change the PLL by an
initcode routine. This is because the
have to be updated to keep the required bit rate constant after the
frequency has changed. It must be ensured that the host does not send
data while the PLL is changing. The initcode examples provided along
with the CCES or VisualDSP++ tools installation demonstrate how this
can be accomplished.
24-58
0 0 0
0
1
24-20, when the UART is enabled,
signal or wait until it has received the four bytes
HWAIT
0
1
ADSP-BF50x Blackfin Processor Hardware Reference
1 1
1
1
and
UARTx_DLL UARTx_DLH
1
0 0
0
goes low,
UA0_RTS
1 0
0
registers
SCLK