Texas Instruments TMS570LS3137 Manual

Texas Instruments TMS570LS3137 Manual

16- and 32-bit risc flash microcontroller
Table of Contents

Advertisement

Quick Links

TMS570LS3137 16- and 32-Bit RISC Flash Microcontroller

1 Device Overview

1.1

Features

1
• High-Performance Automotive-Grade
Microcontroller for Safety-Critical Applications
– Dual CPUs Running in Lockstep
– ECC on Flash and RAM Interfaces
– Built-In Self-Test (BIST) for CPU and On-chip
RAMs
– Error Signaling Module With Error Pin
– Voltage and Clock Monitoring
®
®
• ARM
Cortex
-R4F 32-Bit RISC CPU
– Efficient 1.66 DMIPS/MHz With 8-Stage Pipeline
– FPU With Single- and Double-Precision
– 12-Region Memory Protection Unit (MPU)
– Open Architecture With Third-Party Support
• Operating Conditions
– System Clock up to 180 MHz
– Core Supply Voltage (VCC): 1.2 V Nominal
– I/O Supply Voltage (VCCIO): 3.3 V Nominal
– ADC Supply Voltage (V
• Integrated Memory
– 3MB of Program Flash With ECC
– 256KB of RAM With ECC
– 64KB of Flash With ECC for Emulated
EEPROM
• 16-Bit External Memory Interface
• Common Platform Architecture
– Consistent Memory Map Across Family
– Real-Time Interrupt (RTI) Timer OS Timer
– 96-Channel Vectored Interrupt Module (VIM)
– 2-Channel Cyclic Redundancy Checker (CRC)
• Direct Memory Access (DMA) Controller
– 16 Channels and 32 Control Packets
– Parity Protection for Control Packet RAM
– DMA Accesses Protected by Dedicated MPU
• Frequency-Modulated Phase-Locked Loop
(FMPLL) With Built-In Slip Detector
• Separate Nonmodulating PLL for FlexRay™
• Trace and Calibration Capabilities
– Embedded Trace Macrocell (ETM-R4)
– Data Modification Module (DMM)
– RAM Trace Port (RTP)
– Parameter Overlay Module (POM)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
Sample &
Product
Buy
Folder
): 3.0 to 5.25 V
CCAD
Downloaded From
Tools &
Technical
Software
Documents
SPNS162C – APRIL 2012 – REVISED APRIL 2015
• Multiple Communication Interfaces
– 10/100 Mbps Ethernet MAC (EMAC)
IEEE 802.3 Compliant (3.3-V I/O Only)
Supports MII, RMII, and MDIO
– FlexRay Controller With Two Channels
8KB of Message RAM With Parity Protection
Dedicated Transfer Unit (FTU)
– Three CAN Controllers (DCANs)
64 Mailboxes, Each With Parity Protection
Compliant to CAN Protocol Version 2.0B
– Standard Serial Communication Interface (SCI)
– Local Interconnect Network (LIN) Interface
Controller
Compliant to LIN Protocol Version 2.1
Can be Configured as a Second SCI
– Inter-Integrated Circuit (I
– Three Multibuffered Serial Peripheral Interfaces
(MibSPIs)
128 Words With Parity Protection Each
– Two Standard Serial Peripheral Interfaces
(SPIs)
• Two Next Generation High-End Timer (N2HET)
Modules
– N2HET1: 32 Programmable Channels
– N2HET2: 18 Programmable Channels
– 160-Word Instruction RAM Each With Parity
Protection
– Each N2HET Includes Hardware Angle
Generator
– Dedicated High-End Transfer Unit (HTU) With
MPU for Each N2HET
• Two 12-Bit Multibuffered ADC Modules
– ADC1: 24 Channels
– ADC2: 16 Channels Shared With ADC1
– 64 Result Buffers With Parity Protection Each
• General-Purpose Input/Output (GPIO) Pins
Capable of Generating Interrupts
– Sixteen Pins on the ZWT Package
– Four Pins on the PGE Package
• IEEE 1149.1 JTAG, Boundary Scan and ARM
CoreSight™ Components
• JTAG Security Module
• Packages
– 144-Pin Quad Flatpack (PGE) [Green]
– 337-Ball Grid Array (ZWT) [Green]
Oneyac.com
Support &
Community
TMS570LS3137
2
C)

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the TMS570LS3137 and is the answer not in the manual?

Questions and answers

Subscribe to Our Youtube Channel

Summary of Contents for Texas Instruments TMS570LS3137

  • Page 1: Device Overview

    Community Software Folder Documents TMS570LS3137 SPNS162C – APRIL 2012 – REVISED APRIL 2015 TMS570LS3137 16- and 32-Bit RISC Flash Microcontroller 1 Device Overview Features • High-Performance Automotive-Grade • Multiple Communication Interfaces Microcontroller for Safety-Critical Applications – 10/100 Mbps Ethernet MAC (EMAC) –...
  • Page 2: Applications

    Electronic Stability Control) • Aerospace and Avionics • Electric Power Steering • Railway Communications • HEV and EV Inverter Systems • Off-road Vehicles • Battery Management Systems Device Overview Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 3: Description

    DMIPS. The device supports the word-invariant big-endian [BE32] format. The TMS570LS3137 device has 3MB of integrated flash and 256KB of data RAM. Both the flash and RAM have single-bit error correction and double-bit error detection. The flash memory on this device is a nonvolatile, electrically erasable, and programmable memory implemented with a 64-bit-wide data bus interface.
  • Page 4 RAM or halting the processor to reprogram the data flash. With integrated safety features and a wide choice of communication and control peripherals, the TMS570LS3137 device is an ideal solution for high-performance real-time control applications with safety- critical requirements.
  • Page 5: Functional Block Diagram

    MIBSPI3_nENA SPI4_CLK SPI4_SIMO SPI4 SPI4_SOMI SPI4_nCS0 SPI4_nENA FlexRay MibADC1 MibADC2 N2HET1 N2HET2 MIBSPI5_SIMO[3:0] MIBSPI5_SOMI[3:0] MibSPI5 MIBSPI5_nCS[3:0] MIBSPI5_nENA LIN_RX LIN_TX SCI_RX SCI_TX Figure 1-1. Functional Block Diagram Device Overview Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 6: Table Of Contents

    Clock Monitoring ....... Module Certifications ......... Glitch Filters Mechanical Packaging and Orderable ........ Device Memory Map ..........Information ........6.10 Flash Memory ......Packaging Information Table of Contents Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 7: Revision History

    SPNS162C revision. Scope: Applicable updates to the Hercules™ TMS570 MCU device family, specifically relating to the TMS570LS3137 devices, which are now in the production data (PD) stage of development have been incorporated. Changes from August 1, 2013 to April 30, 2015 (from B Revision (July 2013) to C Revision) Page ..............
  • Page 8 (Die-ID Registers): Updated/Changed the BIT LOCATION column for all ITEM rows ......• Section 9 (Mechanical Packaging and Orderable Information): Updated/Changed section title ........... • Section 9.1 (Packaging Information): Updated/Changed the paragraph Revision History Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 9: Device Comparison

    TMS570LS3137 www.ti.com SPNS162C – APRIL 2012 – REVISED APRIL 2015 3 Device Comparison lists the features of the devices. (1) (2) Table 3-1. TMS570LS3137 Device Comparison FEATURES DEVICES Generic Part Number TMS570LC4357ZWT TMS570LS3137ZWT TMS570LS3137PGE TMS570LS3135ZWT TMS570LS3135PGE TMS570LS1227ZWT Package 337 BGA...
  • Page 10: Terminal Configuration And Functions

    N2HET1[13] N2HET1[06] MIBSPI3NCS[1] Pins can have multiplexed functions. Only the default function is depicted in the figure. Figure 4-1. PGE QFP Package Pinout (144-Pin) Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 11: Zwt Bga Package Ball-Map (337-Ball Grid Array)

    Balls can have multiplexed functions. Only the default function, except for the EMIF signals that are multiplexed with ETM signals, is depicted in the figure. Figure 4-2. ZWT Package Pinout. Top View Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 12: Terminal Functions

    AD1IN[3] Input None ADC1 analog input AD1IN[4] AD1IN[5] AD1IN[6] AD1IN[7] (1) The ADREFHI, ADREFLO, VCCAD and VSSAD connections are common for both ADC cores. Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 13 AD1IN[16] / AD2IN[0] AD1IN[17] / AD2IN[1] AD1IN[18] / AD2IN[2] AD1IN[19] / AD2IN[3] AD1IN[20] / AD2IN[4] AD1IN[21] / AD2IN[5] AD1IN[22] / AD2IN[6] AD1IN[23] / AD2IN[7] Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 14 Programmable, MIBSPI3NCS[3]/I2C_SCL/N2HET1[29] Pullup 20 µA Programmable, N2HET1[30]/MII_RX_DV Pulldown 20 µA Programmable, MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31] Pullup 20 µA Programmable, Disable selected PWM GIOA[5]/EXTCLKIN/N2HET1_PIN_nDIS Pulldown 20 µA outputs Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 15 FRAYRX2 Input Pullup FlexRay data receive (channel 2) Pullup FRAYTX2 Output FlexRay data transmit (channel 2) None FRAYTXEN2 Output FlexRay transmit enable (channel 2) Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 16 SPI4 chip select, or GPIO N2HET1[1]/SPI4NENA/N2HET2[8] SPI4 enable, or GPIO Programmable, Pulldown 20 µA SPI4 slave-input master- N2HET1[2]/SPI4SIMO[0] output, or GPIO SPI4 slave-output master- N2HET1[5]/SPI4SOMI[0]/N2HET2[12] input, or GPIO Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 17 PULL TYPE DESCRIPTION TYPE SIGNAL NAME STATE Programmable, MIBSPI3NCS[1]/N2HET1[25]/MDCLK Output Pullup Serial clock output 20 µA Fixed 20 µA MIBSPI1NCS[2]/N2HET1[19]/MDIO Pullup Serial data input/output Pullup Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 18 Input Pulldown Pulldown to the microcontroller fall out of the specified range. This terminal has a glitch filter. Section 6.8. Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 19 Fixed 100 µA Pullup JTAG test data in Pullup 100 µA Output None JTAG test data out Pulldown Fixed 100 µA Pullup JTAG test select Pullup Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 20 RESET SIGNAL PULL PULL TYPE DESCRIPTION SIGNAL NAME TYPE STATE VCCIO VCCIO VCCIO 3.3-V 3.3-V Operating supply for None Power I/Os VCCIO VCCIO VCCIO Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 21 Table 4-20. PGE Ground Reference for All Supplies Except VCCAD TERMINAL RESET SIGNAL PULL PULL TYPE DESCRIPTION TYPE SIGNAL NAME STATE Ground reference Ground None Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 22 AD1IN[20] / AD2IN[4] AD1IN[21] / AD2IN[5] AD1IN[22] / AD2IN[6] AD1IN[23] / AD2IN[7] (1) The ADREFHI, ADREFLO, VCCAD and VSSAD connections are common for both ADC cores. Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 23 N2HET1[22] N2HET1[23] MIBSPI1NENA/N2HET1[23]/MII_RXD[2] N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0] N2HET1[25] MIBSPI3NCS[1]/N2HET1[25]/MDCLK N2HET1[26]/MII_RXD[1]/RMII_RXD[1] N2HET1[27] MIBSPI3NCS[2]/I2C_SDA/N2HET1[27] N2HET1[28]/MII_RX_CLK/RMII_REFCLK/MII_RX_AVCLK4 N2HET1[29] MIBSPI3NCS[3]/I2C_SCL/N2HET1[29] N2HET1[30]/MII_RX_DV N2HET1[31] MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31] Programmable, Disable selected PWM GIOA[5]/EXTCLKIN/N2HET1_PIN_nDIS Pulldown 20 µA outputs Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 24 EMIF_nCS[3]/RTP_DATA[14]/N2HET2[9] suppression filter with a N2HET1[3]/SPI4NCS[0]/N2HET2[10] programmable duration. EMIF_ADDR[6]/RTP_DATA[13]/N2HET2[11] N2HET1[5]/SPI4SOMI[0]/N2HET2[12] EMIF_ADDR[7]/RTP_DATA[12]/N2HET2[13] N2HET1[7]/N2HET2[14] EMIF_ADDR[8]/RTP_DATA[11]/N2HET2[15] N2HET1[9]/N2HET2[16] N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18] Programmable, Disable selected PWM MIBSPI3NCS[0]/AD2EVT/GIOB[2]/N2HET2_PIN_nDIS Pullup 20 µA outputs Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 25 FlexRay data receive FRAYRX2 Input Pullup Pullup (channel 2) FlexRay data transmit FRAYTX2 Output (channel 2) None None FlexRay transmit enable FRAYTXEN2 Output (channel 2) Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 26 RESET SIGNAL PULL PULL TYPE DESCRIPTION TYPE SIGNAL NAME STATE N2HET1[6]/SCIRX SCI receive, or GPIO Programmable, Pulldown 20 µA N2HET1[13]/SCITX SCI transmit, or GPIO Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 27 SPI4 chip select, or GPIO N2HET1[1]/SPI4NENA/N2HET2[8] SPI4 enable, or GPIO Programmable, Pulldown 20 µA SPI4 slave-input master- N2HET1[2]/SPI4SIMO[0] output, or GPIO SPI4 slave-output master- N2HET1[5]/SPI4SOMI[0]/N2HET2[12] input, or GPIO Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 28 MIBSPI5NCS[2]/DMM_DATA[2] MIBSPI5NCS[3]/DMM_DATA[3] MIBSPI5NENA/DMM_DATA[7]/MII_RXD[3] MibSPI5 enable, or GPIO MIBSPI5SIMO[0]/DMM_DATA[8]/MII_TXD[1]/RMII_TXD[1] Programmable, Pullup 20 µA MIBSPI5SIMO[1]/DMM_DATA[9] MIBSPI5SIMO[2]/DMM_DATA[10] MIBSPI5SIMO[3]/DMM_DATA[11] MibSPI5 slave-in master-out, or GPIO MIBSPI5SOMI[0]/DMM_DATA[12]/MII_TXD[0]/RMII_TXD[0] MIBSPI5SOMI[1]/DMM_DATA[13] MIBSPI5SOMI[2]/DMM_DATA[14] MIBSPI5SOMI[3]/DMM_DATA[15] Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 29 MII output transmit clock Pulldown None N2HET1[10]/MII_TX_CLK/MII_TX_AVCLK4 Transmit clock MIBSPI5SOMI[0]/DMM_DATA[12]/MII_TXD[0]/RMII_TXD[0] MIBSPI5SIMO[0]/DMM_DATA[8]/MII_TXD[1]/RMII_TXD[1] Pullup None Transmit data MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2] Output N2HET1[8]/MIBSPI1SIMO[1]/MII_TXD[3] Pulldown None MIBSPI5CLK/DMM_DATA[4]/MII_TXEN/RMII_TXEN Pullup None Transmit enable Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 30 EMIF address EMIF_ADDR[11]/RTP_DATA[8] Output EMIF_ADDR[12]/RTP_DATA[6] Output EMIF_ADDR[13]/RTP_DATA[5] Output EMIF_ADDR[14]/RTP_DATA[4] Output EMIF_ADDR[15]/RTP_DATA[3] Output EMIF_ADDR[16]/RTP_DATA[2] Output EMIF_ADDR[17]/RTP_DATA[1] Output EMIF_ADDR[18]/RTP_DATA[0] Output EMIF_ADDR[19]/RTP_nENA Output Pulldown EMIF_ADDR[20]/RTP_nSYNC Output EMIF_ADDR[21]/RTP_CLK Output Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 31 STATE ETMDATA[16]/EMIF_DATA[0] ETMDATA[17]/EMIF_DATA[1] ETMDATA[18]/EMIF_DATA[2] ETMDATA[19]/EMIF_DATA[3] ETMDATA[20]/EMIF_DATA[4] ETMDATA[21]/EMIF_DATA[5] ETMDATA[22]/EMIF_DATA[6] ETMDATA[23]/EMIF_DATA[7] Fixed 20 µA Pulldown EMIF Data Pullup ETMDATA[24]/EMIF_DATA[8] ETMDATA[25]/EMIF_DATA[9] ETMDATA[26]/EMIF_DATA[10] ETMDATA[27]/EMIF_DATA[11] ETMDATA[28]/EMIF_DATA[12] ETMDATA[29]/EMIF_DATA[13] ETMDATA[30]/EMIF_DATA[14] ETMDATA[31]/EMIF_DATA[15] Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 32 ETMDATA[13]/EMIF_nOE ETMDATA[14]/EMIF_nDQM[1] Output Pulldown None ETMDATA[15]/EMIF_nDQM[0] ETM data ETMDATA[16]/EMIF_DATA[0] ETMDATA[17]/EMIF_DATA[1] ETMDATA[18]/EMIF_DATA[2] ETMDATA[19]/EMIF_DATA[3] ETMDATA[20]/EMIF_DATA[4] ETMDATA[21]/EMIF_DATA[5] ETMDATA[22]/EMIF_DATA[6] ETMDATA[23]/EMIF_DATA[7] ETMDATA[24]/EMIF_DATA[8] ETMDATA[25]/EMIF_DATA[9] ETMDATA[26]/EMIF_DATA[10] ETMDATA[27]/EMIF_DATA[11] ETMDATA[28]/EMIF_DATA[12] ETMDATA[29]/EMIF_DATA[13] ETMDATA[30]/EMIF_DATA[14] ETMDATA[31]/EMIF_DATA[15] Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 33 EMIF_ADDR[13]/RTP_DATA[5] EMIF_ADDR[12]/RTP_DATA[6] Programmable, EMIF_nCS[4]/RTP_DATA[7] Pullup 20 µA RTP packet data, or GPIO EMIF_ADDR[11]/RTP_DATA[8] EMIF_ADDR[10]/RTP_DATA[9] EMIF_ADDR[9]/RTP_DATA[10] EMIF_ADDR[8]/RTP_DATA[11]/N2HET2[15] Programmable, Pulldown 20 µA EMIF_ADDR[7]/RTP_DATA[12]/N2HET2[13] EMIF_ADDR[6]/RTP_DATA[13]/N2HET2[11] EMIF_nCS[0]/RTP_DATA[15]/N2HET2[7] EMIF_nCS[3]/RTP_DATA[14]/N2HET2[9] Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 34 DMM_DATA[0] DMM_DATA[1] MIBSPI5NCS[2]/DMM_DATA[2] MIBSPI5NCS[3]/DMM_DATA[3] MIBSPI5CLK/DMM_DATA[4]/MII_TXEN/RMII_TXEN MIBSPI5NCS[0]/DMM_DATA[5] Programmable, Pullup MIBSPI5NCS[1]/DMM_DATA[6] 20 µA MIBSPI5NENA/DMM_DATA[7]/MII_RXD[3] DMM data, or GPIO MIBSPI5SIMO[0]/DMM_DATA[8]/MII_TXD[1]/RMII_TXD[1] MIBSPI5SIMO[1]/DMM_DATA[9] MIBSPI5SIMO[2]/DMM_DATA[10] MIBSPI5SIMO[3]/DMM_DATA[11] MIBSPI5SOMI[0]/DMM_DATA[12]/MII_TXD[0]/RMII_TXD[0] MIBSPI5SOMI[1]/DMM_DATA[13] MIBSPI5SOMI[2]/DMM_DATA[14] MIBSPI5SOMI[3]/DMM_DATA[15] Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 35 External clock input #1 Fixed 20 µA Pulldown Pulldown ETMTRACECLKIN/EXTCLKIN2 Input External clock input #2 1.2-V Dedicated core supply for VCCPLL None Power PLLs Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 36 For proper operation – None these terminals must connect FLTP2 only to a test pad or not be connected at all [no connect (NC)]. Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 37 – None – None – None – None – None – None – None – None – None – None – None – None Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 38 Table 4-43. ZWT Supply for Core Logic: 1.2-V Nominal TERMINAL RESET SIGNAL PULL PULL TYPE DESCRIPTION TYPE SIGNAL NAME STATE 1.2-V None Core supply Power Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 39 VCCIO VCCIO VCCIO VCCIO VCCIO 3.3-V VCCIO None Operating supply for I/Os Power VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 40 Table 4-45. ZWT Ground Reference for All Supplies Except VCCAD TERMINAL RESET SIGNAL PULL PULL TYPE DESCRIPTION TYPE SIGNAL NAME STATE Ground None Ground reference Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 41: Specifications

    (2) To avoid significant degradation, the device power-on hours (POH) must be limited to those specified in this table. To convert to equivalent POH for a specific temperature profile, see the Calculating Equivalent Power-on-Hours for Hercules Safety MCUs Application Report (SPNA207). Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 42: Recommended Operating Conditions

    , which is with respect to V CCAD SSAD (2) Reliability data is based upon a temperature profile that is equivalent to 100,000 power-on hours at 105°C junction temperature. Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 43: Switching Characteristics For Clock Domains

    180 MHz for the ZWT package, with one address wait state and three data wait states. The flash wrapper defaults to nonpipelined mode with zero address wait state and one random-read data wait state. Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 44: Power Consumption

    (4) LBIST and PBIST currents are for a short duration, typically less than 10 ms. They are usually ignored for thermal calculations for the device and the voltage regulator Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From...
  • Page 45: Input/Output Electrical Characteristics

    Output capacitance (1) Source currents (out of the device) are negative while sink currents (into the device) are positive. (2) This does not apply to the nPORRST pin. Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 46: Thermal Resistance Characteristics

    Junction-to-board thermal resistance 14.1 RΘ Junction-to-case thermal resistance Junction-to-package top, Still air (includes 5x5 thermal via cluster in 2s2p Ψ 0.33 PCB connected to 1st ground plane) Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 47: Output Buffer Drive Strengths

    (1) Either SPI2PC9[11] or SPI2PC9[24] can change the output strength of the SPI2SOMI pin. In case of a 32-bit write where these two bits differ, SPI2PC9[11] determines the drive strength. Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From...
  • Page 48: Input Timings

    CL = 100 pF CL = 150 pF CL = 15 pF CL = 50 pF Fall time, t CL = 100 pF CL = 150 pF Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 49 (1) This specification does not account for any output buffer drive strength differences or any external capacitive loading differences. Check Table 5-4 for output buffer drive strength information on each signal. Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 50: Low-Emi Output Buffers

    IOH / IOL specifications. The low-EMI output buffers are automatically configured to be in the standard buffer mode when the device enters a low-power mode. Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 51 GPREG1.6 Module: ETM GPREG1.7 Signal: TMS GPREG1.8 Signal: TDI GPREG1.9 Signal: TDO GPREG1.10 Signal: RTCK GPREG1.11 Signal: TEST GPREG1.12 Signal: nERROR GPREG1.13 Reserved GPREG1.14 Module: RTP GPREG1.15 Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 52: System Information And Electrical Specifications

    (after normal power-up). No register or memory contents are preserved in the core domains that are turned off. System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From...
  • Page 53: Voltage Monitor Characteristics

    Table 6-2. VMON Supply Glitch Filtering Capability PARAMETER UNIT Width of glitch on VCC that can be filtered 1000 Width of glitch on VCCIO that can be filtered 1000 System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 54: Power Sequencing And Power On Reset

    3517 oscillator cycles The CPU reset is released at the end of the sequence in Table 6-3 and fetches the first instruction from address 0x00000000. System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 55 NOTE: There is no timing dependency between the ramp of the VCCIO and the VCC supply voltage; this is just an exemplary drawing. Figure 6-1. nPORRST Timing Diagram System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From...
  • Page 56: Warm Reset (Nrst)

    MAX will generate a reset. See Section 6.8. (1) Assumes the oscillator has started up and stabilized before nPORRST is released . System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 57: Arm-R4F Cpu Information

    CPU1 = "north" orientation, CPU2 = "flip west" orientation • dedicated guard ring for each CPU Flip West North Figure 6-2. Dual-CPU Orientation System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 58 Complete isolation of the self-tested CPU core from rest of the system during the self-test run • Ability to capture the Failure interval number • Time-out counter for the CPU self-test run as a fail-safe feature System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 59 17745 87.16 19110 87.61 20475 87.98 21840 88.38 23205 88.69 24570 88.98 25935 89.28 27300 89.50 28665 89.76 30030 90.01 31395 90.21 32760 System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 60: Clocks

    Note A: The values of C1 and C2 should be provided by the resonator/crystal vendor. Note B: Kelvin_GND should not be connected to any other GND. Figure 6-4. Recommended Crystal/Clock Connection System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 61 Pulse duration, OSCIN low (when input to the OSCIN is a square wave) w(OSCIL) Pulse duration, OSCIN high (when input to the OSCIN is a square wave) w(OSCIH) System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 62 Untrimmed frequency LPO - LF oscillator Startup time from STANDBY (LPO BIAS_EN High for µs at least 900µs) LFLPO cold startup time 2000 µs System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 63 PLL2 Reference Clock frequency INTCLK2 Post-ODCLK – PLL2 Post-divider input clock frequency post_ODCLK2 VCOCLK – PLL2 Output Divider (OD) input clock frequency VCOCLK2 System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 64 Is disabled via the CDDISx registers bit 4 VCLKA2 VCLK VCLKASRC • Defaults to VCLK as the source • Is disabled via the CDDISx registers bit 5 System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 65 Application can ensure this by programming the RTI1DIV field of the RCLKSRC register, if necessary • Is disabled via the CDDISx registers bit 6 System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 66 Resolution Clock EXTCLKIN1 NTU[3] CAN Baud Rate PLL#2 output NTU[2] N2HETx Start of cycle NTU[1] DCANx Macro Tick NTU[0] Figure 6-7. Device Clock Domains System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 67 Reserved 1010 Reserved 1011 VCLKA1 1011 Reserved 1100 VCLKA2 1100 Reserved 1101 Reserved 1101 Reserved 1110 VCLKA4 1110 Reserved 1111 Reserved 1111 Reserved System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 68: Clock Monitoring

    The counter blocks start counting down from their seed values at the same time; a mismatch from the expected frequency for the clock under test generates an error signal which is used to interrupt the CPU. System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From...
  • Page 69 Table 6-18. DCC2 Counter 1 Clock Sources KEY [3:0] CLOCK SOURCE [3:0] CLOCK NAME others N2HET2[0] 00x0 - 0x7 Reserved 0x8 - 0xF VCLK System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 70: Glitch Filters

    (1) The glitch filter design on the nPORRST signal is designed such that no size pulse will reset any part of the microcontroller (flash pump, I/O pins, and so forth) without also generating a valid reset signal to the CPU. System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From...
  • Page 71: Device Memory Map

    RESERVED 0x002FFFFF Flash (3MB) 0x00000000 Figure 6-9. TMS570LS3137 Memory Map The Flash memory is mirrored to support ECC logic testing. The base address of the mirrored Flash image is 0x2000 0000. System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated...
  • Page 72 0xFCF788FF 256B 256B No error (Ethernet Wrapper) Ethernet MDIO 0xFCF78900 0xFCF789FF 256B 256B No error Interface EMIF Registers 0xFCFFE800 0xFCFFE8FF 256B 256B Abort System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 73 Reads: 0, writes: no effect DCAN1 PS[8] 0xFFF7DC00 0xFFF7DDFF 512B 512B Reads: 0, writes: no effect DCAN2 PS[8] 0xFFF7DE00 0xFFF7DFFF 512B 512B Reads: 0, writes: no effect System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 74 Reads: 0, writes: no effect System Module - Frame 1 (see device PPS7 0xFFFFFF00 0xFFFFFFFF 256B 256B Reads: 0, writes: no effect TRM) System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 75 The device contains dedicated logic to generate a bus error response on any access to a module that is in a power domain that has been turned OFF. System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From...
  • Page 76 TO flag, so that any further aborts are not misinterpreted as having been caused due to a time-out from the POM. System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From...
  • Page 77: Flash Memory

    (2) The flash bank7 can be programmed while executing code from flash bank0 or bank1. (3) Code execution is not allowed from flash bank7. System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From...
  • Page 78 (2) During bank erase, the selected sectors are erased simultaneously. The time to erase the bank is specified as equal to the time to erase a sector. System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From...
  • Page 79 (2) During bank erase, the selected sectors are erased simultaneously. The time to erase the bank is specified as equal to the time to erase a sector. System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From...
  • Page 80: Tightly Coupled Ram (Tcram) Interface Module

    Error Signaling Module. The module also captures the peripheral RAM address that caused the parity error. System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From...
  • Page 81 The CPU read access gets the actual data from the peripheral. The application can choose to generate an interrupt whenever a peripheral RAM parity error is detected. System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From...
  • Page 82: On-Chip Sram Initialization And Testing

    (3) ESRAM5: Address 0x08010000 - 0x0801FFFF (RAM power domain 1) (4) ESRAM6: Address 0x08020000 - 0x0802FFFF (RAM power domain 2) (5) ESRAM8: Address 0x08030000 - 0x0803FFFF (RAM power domain 3) System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 83 AND (ii) The application must poll for the "BUF INIT ACTIVE" status flag in the SPIFLG register to become cleared (zero) (3) Reserved only. The FlexRay RAM has its own initialization mechanism. System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 84: External Memory Interface (Emif)

    Data bus parking 6.14.2 Electrical and Timing Specifications 6.14.2.1 Asynchronous RAM EMIF_nCS[3:2] EMIF_BA[1:0] EMIF_ADDR[21:0] EMIF_nDQM[1:0] EMIF_nOE EMIF_DATA[15:0] EMIF_nWE Figure 6-11. Asynchronous Memory Read Timing System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 85 EMIF_nOE EMIF_WAIT Asserted Deasserted Figure 6-12. EMIFnWAIT Read Timing Requirements EMIF_nCS[3:2] EMIF_BA[1:0] EMIF_ADDR[21:0] EMIF_nDQM[1:0] EMIF_nWE EMIF_DATA[15:0] EMIF_nOE Figure 6-13. Asynchronous Memory Write Timing System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 86 MEWC in the Asynchronous Wait Cycle Configuration Register. See the TMS570LS31X/21X Technical Reference Manual (SPNU499) for more information. System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From...
  • Page 87 Output hold time, EMIFnWE high h(EMWEH-EMBAIV) (WH)*E-4 (WH)*E (WH)*E+3 to EMIFBA[1:0] invalid Output setup time, su(EMAV-EMWEL) EMIFADDR[21:0] valid to (WS)*E-4 (WS)*E (WS)*E+3 EMIFnWE low System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 88 6.14.2.2 Synchronous Timing BASIC SDRAM READ OPERATION EMIF_CLK EMIF_nCS[0] EMIF_nDQM[1:0] EMIF_BA[1:0] EMIF_ADDR[21:0] 2 EM_CLK Delay EMIF_DATA[15:0] EMIF_nRAS EMIF_nCAS EMIF_nWE Figure 6-15. Basic SDRAM Read Operation System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 89 EMIFBA[1:0] valid Output hold time, EMIF_CLK rising to oh(CLKH-AIV) EMIFADDR[21:0] and EMIFBA[1:0] invalid Delay time, EMIF_CLK rising to EMIFDATA[15:0] d(CLKH-DV) valid System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 90 Output hold time, EMIF_CLK rising to EMIFnWE oh(CLKH-WEIV) invalid Delay time, EMIF_CLK rising to EMIFDATA[15:0] dis(CLKH-DHZ) tri-stated Output hold time, EMIF_CLK rising to ena(CLKH-DLZ) EMIFDATA[15:0] driving System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 91: Vectored Interrupt Manager

    ESM Low level interrupt SYSTEM Software interrupt (SSI) PMU Interrupt GPIO GPIO interrupt B N2HET1 N2HET1 level 1 interrupt HTU1 HTU1 level 1 interrupt System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 92 I2C level 0 interrupt Reserved Reserved 67-72 N2HET2 N2HET2 level 1 interrupt SCI level 1 interrupt HTU2 HTU2 level 1 interrupt Ethernet C0_MISC_PULSE Ethernet C0_TX_PULSE System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 93 The application can change the mapping of interrupt sources to the interrupt channels via the interrupt channel control registers (CHANCTRLx) inside the VIM module. System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From...
  • Page 94: Dma Controller

    8-, 16-, 32-, or 64-bit transactions supported • Multiple addressing modes for source/destination (fixed, increment, offset) • Auto-initiation • Power-management mode • Memory Protection with four configurable memory regions System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 95 MIBSPI1[15] / MIBSPI3[15] / SCI transmit / DMAREQ[31] MIBSPI5[0] (1) SPI1, SPI3, SPI5 receive in standard SPI mode (2) SPI1, SPI3, SPI5 transmit in standard SPI mode System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 96: Real Time Interrupt Module

    Capture free running counter up counter RTICAFRCx RTICAUCx CAP event source 0 External control CAP event source 1 Figure 6-17. Counter Block Diagram System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 97 Table 6-33. Table 6-33. Network Time Synchronization Inputs NTU Input Source Macrotick Start of Cycle PLL2 Clock output EXTCLKIN1 clock input System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 98: Error Signaling Module

    DMA/DMM - imprecise write error Group1 FTU - parity Group1 VIM RAM - parity Group1 FTU - MPU Group1 MibSPI1 - parity Group1 MibSPI3 - parity Group1 System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 99 Group1 Reserved Group1 Reserved Group1 Reserved Group1 Reserved Group1 Reserved Group1 Reserved Group1 Reserved Group1 Reserved Group1 Reserved Group1 DCC2 - error Group1 System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 100 FMC - uncorrectable error: bus1 and bus2 interfaces Group3 (does not include address parity error and errors on accesses to EEPROM bank) Reserved Group3 Reserved Group3 Reserved Group3 Reserved Group3 System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 101 Group3 Reserved Group3 Reserved Group3 Reserved Group3 Reserved Group3 Reserved Group3 Reserved Group3 Reserved Group3 Reserved Group3 Reserved Group3 Reserved Group3 Reserved Group3 System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 102: Reset / Abort / Error Sources

    (1) The Undefined Instruction TRAP is NOT detectable outside the CPU. The trap is taken only if the instruction reaches the execute stage of the CPU. System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From...
  • Page 103 ESM => NMI => nERROR Memory parity error User/Privilege 1.15 VOLTAGE MONITOR VMON out of voltage range Reset CPU SELFTEST (LBIST) CPU Selftest (LBIST) error User/Privilege 1.27 System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 104: Digital Windowed Watchdog

    The watchdog is disabled by default and must be enabled by the application. Once enabled, the watchdog can only be disabled upon a system reset. System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From...
  • Page 105: Debug Subsystem

    Reads: 0, writes: no effect 6.21.3 JTAG Identification Code The JTAG ID code for this device is the same as the device ICEPick Identification Code. System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 106 Table 6-39. Debug ROM table ADDRESS DESCRIPTION VALUE 0x000 pointer to Cortex-R4F 0x00001003 0x001 ETM-R4 0x00002003 0x002 TPIU 0x00003003 0x003 0x00004003 0x004 end of table 0x00000000 System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 107 Delay time, TDO valid after RTCK fall (RTCKf) (1) Timings for TDO are specified for a maximum of 50pF load on TDO RTCK Figure 6-20. JTAG Timing System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 108 A secure device only permits JTAG accesses to the AJSM scan chain via the Secondary Tap # 2 of the ICEPick module. All other secondary taps, test taps and the boundary scan interface are not accessible in this state. System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 109 Clock period cyc(ETM) (HCLK) Low pulse width l(ETM) High pulse width h(ETM) Clock and data rise time r(ETM) Clock and data fall time f(ETM) System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 110 Delay time, ETM trace clock low to ETM d(ETMTRACECLKl-ETMDATAV) data valid NOTE The ETMTRACECLK and ETMDATA timing is based on a 15-pF load and for ambient temperature lower than 85°C. System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 111 HCLK / 2 High pulse width )/2) - ((t )/2) h(RTP) cyc(RTP) Low pulse width )/2) - ((t )/2) l(RTP) cyc(RTP) System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 112 RTPnENA goes low before a packet that + 12 ena(RTP) c(HCLK) r(RTPSYNC) c(HCLK) r(RTPSYNC) has been halted, resumes System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 113 Pulse duration, DMMCLK low )/2) - ((t )/2) l(DMM) cyc(DMM) ssu(DMM) sh(DMM) DMMSYNC DMMCLK DMMDATA dsu(DMM) dh(DMM) Figure 6-28. DMMDATA Timing System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 114 D5x, D6x, D7x. Packet D8 would result in an overflow. Once DMMnENA is asserted, the DMM expects to stop receiving packets after 4 HCLK cycles; once DMMnENA is deasserted, the DMM can handle packets immediately (after 0 HCLK cycles). System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 115 RTCK BSDL Figure 6-30. Boundary Scan Implementation (Conceptual Diagram) Data is serially shifted into all boundary-scan buffers via TDI, and out via TDO. System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 116: Peripheral Information And Electrical Specifications

    12 bits Monotonic Assured ≤ AD ≥ AD Output conversion code 00h to FFFh [00 for V ; FFF for V REFLO REFHI Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 117 RTI module. That is, the interrupt condition can be used as a trigger source even if the actual interrupt is not signaled to the CPU. Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From...
  • Page 118 RTI module. That is, the interrupt condition can be used as a trigger source even if the actual interrupt is not signaled to the CPU. Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From...
  • Page 119 If 30[0] = 1, then the default MibADC2 event trigger hook-up is used. If 30[0] = 0 and 30[1] = 1, then the alternate MibADC2 event trigger hook-up is used. Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From...
  • Page 120 RTI module. That is, the interrupt condition can be used as a trigger source even if the actual interrupt is not signaled to the CPU. Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From...
  • Page 121 (1) If a shared channel is being converted by both ADC converters at the same time, the on-state leakage is equal to I AOSL1 AOSL2 Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 122 (3) This is the minimum sample/hold and conversion time that can be achieved. These parameters are dependent on many factors, for example, the prescale settings. Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From...
  • Page 123 – AD )/ 2 for 10-bit mode REFHI REFLO (2) 1 LSB = (AD – AD )/ 2 for 12-bit mode REFHI REFLO Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 124 0 ... 000 Analog Input Value (LSB) NOTE A: 1 LSB = (AD – AD REFHI REFLO Figure 7-2. Differential Nonlinearity (DNL) Error Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 125 0 ... 000 Analog Input Value (LSB) NOTE A: 1 LSB = (AD – AD REFHI REFLO Figure 7-3. Integral Nonlinearity (INL) Error Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 126 0 ... 000 Analog Input Value (LSB) NOTE A: 1 LSB = (AD – AD REFHI REFLO Figure 7-4. Absolute Accuracy (Total) Error Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 127: General-Purpose Input/Output

    • Internal pullup/pulldown allows unused I/O pins to be left unconnected For information on input and output timings see Section 5.11 Section 5.12 Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 128: Enhanced High-End Timer (N2Het)

    7.4.3 Input Timing Specifications The N2HET instructions PCNT and WCAP impose some timing constraints on the input signals. N2HETx Figure 7-5. N2HET Input Capture Timings Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 129 ENHANCED PULSE CAPTURE N2HET1[00] N2HET1[01] N2HET1[02] N2HET1[03] N2HET1[04] N2HET1[05] N2HET1[06] N2HET1[07] N2HET1[08] N2HET1[09] N2HET1[10] N2HET1[11] N2HET1[12] N2HET1[13] N2HET1[14] N2HET1[15] N2HET1[16] N2HET1[17] N2HET1[18] N2HET1[19] N2HET1[20] Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 130 However, anytime the slave receives the resynchronization signal from the master, the slave must synchronize itself again.. N2HET1 N2HET2 NHET_LOOP_SYNC EXT_LOOP_SYNC NHET_LOOP_SYNC EXT_LOOP_SYNC Figure 7-6. N2HET1 – N2HET2 Synchronization Hookup Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 131 "N2HET Pin Disable" feature. GIOA[5] is connected to the "Pin Disable" input for N2HET1, and GIOB[2] is connected to the "Pin Disable" input for N2HET2. Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 132 HTUREQ[2] HTU2 DCP[2] N2HET2 HTUREQ[3] HTU2 DCP[3] N2HET2 HTUREQ[4] HTU2 DCP[4] N2HET2 HTUREQ[5] HTU2 DCP[5] N2HET2 HTUREQ[6] HTU2 DCP[6] N2HET2 HTUREQ[7] HTU2 DCP[7] Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 133: Flexray Interface

    Input minimum pulse width to meet the FlexRay sampling + 2.5 c(AVCLK2) requirement (1) t parameter RxAsymDelay CCIO Input 0.6*V 0.6*V CCIO CCIO 0.4*V 0.4*V CCIO CCIO Figure 7-8. FlexRay Inputs Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 134 Peripheral Power Down Registers of the System Module before accessing any FlexRay module register. For more information on the FTU, see the TMS570LS31x/TMS570LS21x 16/32-Bit RISC Flash Microcontroller Technical Reference Manual (SPNU499). Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 135: Controller Area Network (Dcan)

    Delay time, transmit shift register to CANnTX pin d(CANnTX) Delay time, CANnRX pin to receive shift register d(CANnRX) (1) These values do not include rise/fall times of the output buffer. Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 136: Local Interconnect Network Interface (Lin)

    – Optional baudrate update – Synchronization Validation • programmable transmission rates with 7 fractional bits • Error detection • 2 Interrupt lines with priority encoding Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 137: Serial Communication Interface (Sci)

    Four error flags and five status flags provide detailed information regarding SCI events. • Capability to use DMA for transmit and receive data. Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 138: Inter-Integrated Circuit (I2C)

    The combined format in 10-bit address mode (the I2C module sends the slave address second byte every time it sends the slave address first byte) Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From...
  • Page 139 = The total capacitance of one bus line in pF. w(SDAH) su(SDA-SCLH) w(SP) w(SCLL) su(SCLH-SDAH) w(SCLH) r(SCL) c(SCL) f(SCL) h(SCLL-SDAL) h(SDA-SCLL) su(SCLH-SDAL) h(SCLL-SDAL) Stop Start Repeated Start Stop Figure 7-9. I2C Timings Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 140 + t su(SDA-SCLH) • = total capacitance of one bus line in pF. If mixed with fast-mode devices, faster fall- times are allowed. Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 141: Multibuffered / Standard Serial Peripheral Interface

    For example, up to 15 trigger sources are available which can be used by each transfer group. These trigger options are listed in Table 7-21 for MIBSPI1, Section 7.10.3.2 MIBSPI3 and Section 7.10.3.3 for MibSPI5. Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 142 0011 GIOA[2] EVENT3 0100 GIOA[3] EVENT4 0101 GIOA[4] EVENT5 0110 GIOA[5] EVENT6 0111 GIOA[6] EVENT7 1000 GIOA[7] EVENT8 1001 HET[8] EVENT9 1010 N2HET1[10] Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 143 (at the N2HET1 module boundary). This way, a trigger condition can be generated even if the N2HET1 signal is not selected to be output on the pad. Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 144 GIOx signal, then care must be taken to disable GIOx from triggering MibSPI5 transfers; there is no multiplexing on the input connections. Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From...
  • Page 145 (5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17). (6) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From...
  • Page 146 SPICLK (clock polarity=1) SPISIMO Master Out Data Is Valid SPICSn SPIENAn Figure 7-11. SPI Master Mode Chip Select Timing (CLOCK PHASE = 0) Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 147 (5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17). (6) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From...
  • Page 148 SPICLK (clock polarity=1) SPISIMO Master Out Data Is Valid SPICSn SPIENAn Figure 7-13. SPI Master Mode Chip Select Timing (CLOCK PHASE = 1) Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 149 = 2t ≥ 40ns. c(SPC)S c(VCLK) (6) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17). Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 150 Figure 7-14. SPI Slave Mode External Timing (CLOCK PHASE = 0) SPICLK (clock polarity=0) SPICLK (clock polarity=1) SPIENAn SPICSn Figure 7-15. SPI Slave Mode Enable Timing (CLOCK PHASE = 0) Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 151 = 2t ≥ 40ns. c(SPC)S c(VCLK) (6) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17). Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 152 (clock polarity=0) SPICLK (clock polarity=1) SPIENAn SPICSn SPISOMI Slave Out Data Is Valid Figure 7-17. SPI Slave Mode Enable Timing (CLOCK PHASE = 1) Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 153: Ethernet Media Access Controller

    - MIIRXD) Hold time, MII_RX_DV valid after MII_RX_CLK rising edge h(MIIRXCLKH - MIIRXDV) Hold time, MII_RX_ER valid after MII_RX_CLK rising edge h(MIIRXCLKH - MIIRXER) Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 154 UNIT Delay time, MII_TX_CLK rising edge to MII_TXD[3:0] valid d(MIIRXCLKH - MIITXD) Delay time, MII_TX_CLK rising edge to MII_TXEN valid d(MIIRXCLKH - MIITXEN) Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 155 Table 7-31. Switching Characteristics Over Recommended Operating Conditions for EMAC RMII Transmit PARAMETER UNIT Output delay time, RMII_REFCLK high to RMII_TXD[1:0] valid d(REFCLK-TXD) Output delay time, RMII_REFCLK high to RMII_TXEN valid d(REFCLK-TXEN) Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 156 Table 7-33. MDIO Output Timing Requirements UNIT tc(MDCLK) Cycle time, MDCLK – Delay time, MDCLK low to MDIO data output td(MDCLKL-MDIO) –7 valid Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 157: Device And Documentation Support

    Device Support 8.1.1 Development Support Texas Instruments (TI) offers an extensive line of development tools for the TMS570LSxRM48Lx family of MCUs, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules.
  • Page 158 Q = –40 C to 125 C Quality Designator: Q1 = Automotive Shipping Options: R = Tape and Reel Figure 8-1. TMS570LS3137 Device Numbering Conventions Device and Documentation Support Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From...
  • Page 159: Documentation Support

    All other trademarks are the property of their respective owners. Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
  • Page 160: Device Identification Code Register

    Program memory with ECC RAM ECC Indicates if RAM memory ECC is present. ECC implemented REVISION Revision of the device. The platform family ID is always 0b101 Device and Documentation Support Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 161: Die Identification Registers

    Y Coord. on Wafer 0xFFFFFF7C[23:12] Wafer # 0xFFFFFF7C[31:24] Lot # 0xFFFFFF80[23:0] Reserved 0xFFFFFF80[31:24] Module Certifications The following communications modules have received certification of adherence to a standard. Device and Documentation Support Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 162 TMS570LS3137 SPNS162C – APRIL 2012 – REVISED APRIL 2015 www.ti.com 8.9.1 FlexRay™ Certifications Figure 8-3. FlexRay Certification for ZWT Package Device and Documentation Support Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 163 TMS570LS3137 www.ti.com SPNS162C – APRIL 2012 – REVISED APRIL 2015 Figure 8-4. FlexRay Certification for PGE Package Device and Documentation Support Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 164 TMS570LS3137 SPNS162C – APRIL 2012 – REVISED APRIL 2015 www.ti.com 8.9.2 DCAN Certification Figure 8-5. DCAN Certification Device and Documentation Support Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 165 TMS570LS3137 www.ti.com SPNS162C – APRIL 2012 – REVISED APRIL 2015 8.9.3 LIN Certification 8.9.3.1 LIN Master Mode Figure 8-6. LIN Certification - Master Mode Device and Documentation Support Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 166 SPNS162C – APRIL 2012 – REVISED APRIL 2015 www.ti.com 8.9.3.2 LIN Slave Mode - Fixed Baud Rate Figure 8-7. LIN Certification - Slave Mode - Fixed Baud Rate Device and Documentation Support Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 167 SPNS162C – APRIL 2012 – REVISED APRIL 2015 8.9.3.3 LIN Slave Mode - Adaptive Baud Rate Figure 8-8. LIN Certification - Slave Mode - Adaptive Baud Rate Device and Documentation Support Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 168: Mechanical Packaging And Orderable Information

    This data is subject to change without notice and without revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Mechanical Packaging and Orderable Information Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Downloaded From Oneyac.com...
  • Page 169 PACKAGE OPTION ADDENDUM www.ti.com 23-Nov-2021 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples Drawing Ball material (4/5) TMS5703137CGWTMEP ACTIVE NFBGA Non-RoHS SNPB Level-3-220C-168 HR -55 to 125 TMS570 &...
  • Page 170 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TMS570LS3137, TMS570LS3137-EP : •...
  • Page 171 PACKAGE MATERIALS INFORMATION www.ti.com 5-Jan-2022 TRAY Chamfer on Tray corner indicates Pin 1 orientation of packed units. *All dimensions are nominal Device Package Package Pins SPQ Unit array L (mm) Name Type matrix temperature (mm) (µm) (mm) (mm) (mm) (°C) TMS5703137CGWTME NFBGA 6 X 15...
  • Page 172 PACKAGE OUTLINE ZWT0337A NFBGA - 1.4 mm max height SCALE 0.950 PLASTIC BALL GRID ARRAY 16.1 15.9 BALL A1 CORNER 16.1 15.9 1.4 MAX SEATING PLANE 0.45 BALL TYP 0.12 C 0.35 14.4 TYP (0.8) TYP SYMM (0.8) TYP 14.4 SYMM 0.55 337X...
  • Page 173 DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS NOT TO SCALE 4223381/A 02/2017 NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99). www.ti.com Downloaded From Oneyac.com...
  • Page 174 EXAMPLE STENCIL DESIGN ZWT0337A NFBGA - 1.4 mm max height PLASTIC BALL GRID ARRAY ( 0.4) TYP (0.8) TYP 10 11 12 13 14 15 16 17 18 19 (0.8) TYP SYMM SYMM SOLDER PASTE EXAMPLE BASED ON 0.15 mm THICK STENCIL SCALE:7X 4223381/A 02/2017 NOTES: (continued)
  • Page 175 MECHANICAL DATA MTQF017A – OCTOBER 1994 – REVISED DECEMBER 1996 PGE (S-PQFP-G144) PLASTIC QUAD FLATPACK 0,27 0,08 0,17 0,50 0,13 NOM Gage Plane 17,50 TYP 20,20 19,80 0,25 0,05 MIN 22,20 0 – 7 21,80 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040147 / C 10/96...
  • Page 176 TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2022, Texas Instruments Incorporated Downloaded From Oneyac.com...
  • Page 177 单击下面可查看定价,库存,交付和生命周期等信息 >>TI(德州仪器) Downloaded From Oneyac.com...

Table of Contents