Interrupt Priority; Interrupt Masking & Control; Interrupt Mask Register (Imask) - Analog Devices ADSP-2106x SHARC User Manual

Program Sequencing
3.6.4

Interrupt Priority

The interrupt bits in IRPTL are ordered by priority. The interrupt
priority is from 0 (highest) to 31 (lowest). Interrupt priority determines
which interrupt is serviced first when more than one occurs in the
same cycle. It also determines which interrupts are nested when
nesting is enabled (see "Interrupt Nesting and IMASKP").
The arithmetic interrupts—fixed-point overflow and floating-point
overflow, underflow, and invalid operation—are determined from
flags in the sticky status register (STKY). By reading these flags, the
service routine for one of these interrupts can determine which
condition caused the interrupt. The routine also has to clear the
appropriate STKY bit so that the interrupt is not still active after the
service routine is done.
The timer decrementing to zero causes both interrupt 4 and interrupt
14. This feature allows you to choose the priority of the timer interrupt.
Unmask the timer interrupt that has the priority you want, and leave
the other one masked. Unmasking both interrupts results in two
interrupts when the timer reaches zero. In this case the processor
services the higher priority interrupt first, then the lower priority
interrupt.
3.6.5 Interrupt Masking & Control
All interrupts except for reset can be enabled and disabled by the
global interrupt enable bit, IRPTEN, bit 12 in the MODE1 register. This
bit is cleared at reset. You must set this bit for interrupts to be enabled.

3.6.5.1 Interrupt Mask Register (IMASK)

All interrupts except for reset can be masked. Masked means the
interrupt is disabled. Interrupts that are masked are still latched (in
IRPTL), so that if the interrupt is later unmasked, it is processed.
The IMASK register controls interrupt masking. The bits in IMASK
correspond exactly to the bits in the IRPTL register. For example, bit 10
in IMASK masks or unmasks the same interrupt latched by bit 10 in
IRPTL.
– If a bit in IMASK is set to 1, its interrupt is unmasked (enabled).
– If the bit is cleared (to 0), the interrupt is masked (disabled).
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