Interrupt Mask Register (Imask - Analog Devices SHARC ADSP-21368 Hardware Reference Manual

Interrupt Registers
Table B-5. Interrupt Latch (IRPTL) Register Bit Descriptions (Cont'd)
Bit Name
27 EMULI
28 SFT0I
29 SFT1I
30 SFT2I
31 SFT3I

Interrupt Mask Register (IMASK)

The register is a non-memory-mapped, universal, system register
IMASK
( and
Ureg Sreg
in the register corresponds to a bit with the same name in the
IMASK
registers. The bits in the
mask (disable if cleared, = 0) the interrupts that are latched in the
register. Except for
When the
IMASK
cessor's response to the interrupt. The
interrupt even when masked, and the processor responds to that latched
interrupt if it is later unmasked.
provide bit definitions for the
B-18
Description
Emulator (Lower Priority) Interrupt. Indicates if an EMULI is
latched and is pending (if set, = 1), or no EMULI is pending (if
cleared, = 0). An EMULI occurs on reset and when an external device
asserts the EMU pin. This interrupt has a lower priority than
EMULI, but higher priority than software interrupts.
User Software Interrupt 0. Indicates if a SFT0I is latched and is
pending (if set, = 1), or no SFT0I is pending (if cleared, = 0). An
SFT0I interrupt occurs when a program sets (= 1) this bit.
User Software Interrupt 1. Indicates if a SFT1I is latched and is
pending (if set, = 1), or no SFT1I is pending (if cleared, = 0). An
SFT1I interrupt occurs when a program sets (= 1) this bit.
User Software Interrupt 2. Indicates if a SFT2I is latched and is
pending (if set, = 1), or no SFT2I is pending (if cleared, = 0). An
SFT2I interrupt occurs when a program sets (= 1) this bit.
User Software Interrupt 3. Indicates if a SFT3I is latched and is
pending (if set, = 1), or no SFT3I is pending (if cleared, = 0). An
SFT3I interrupt occurs when a program sets (= 1) this bit.
). The reset value for this register is 0x0000 0003. Each bit
register unmask (enable if set, = 1), or
IMASK
and
RSTI EMUI
register masks an interrupt, the masking disables the pro-
Figure
IMASK
ADSP-21368 SHARC Processor Hardware Reference
, all interrupts are maskable.
register still latches an
IRPTL
B-3, Figure B-4
register.
IRPTL
IRPTL
and Table B-6