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Motorola PowerPC PowerQUICC II MPC8260 User Manual
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Motorola PowerPC PowerQUICC II MPC8260 User Manual

Motorola PowerPC PowerQUICC II MPC8260 User Manual

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3/1999
Rev 0.1
™
MPC8260 PowerQUICC II
ADS User's Manual
™

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Summary of Contents for Motorola PowerPC PowerQUICC II MPC8260

  • Page 1 3/1999 Rev 0.1 ™ MPC8260 PowerQUICC II ADS User’s Manual ™...
  • Page 2 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages.

  • Page 3: Table Of Contents

    DS2 - SDRAM DIMM Configuration Memory I2C Slave Address Switch ..24 3.2.7 DS3 - Software Options Switch ................ 24 3.2.8 J1 - VPP Source Selector .................. 25 3.2.9 J2 - IDDL Measurement..................25 3.2.10 J3 - Optional Ventilator Supply ................ 25 MOTOROLA Contents...
  • Page 4 4.2.2 ATM UNI Interrupt ...................37 Clock Generator.....................37 Bus Configuration....................38 4.4.1 Single MPC8260 Mode ..................38 4.4.2 60x Bus Mode....................38 Buffering........................38 Chip - Select Generator ..................38 Synchronous Dram DIMM (60X Bus) ..............39 4.7.1 SDRAM Programming..................41 MPC8260 PowerQUICC II ADS User’s Manual MOTOROLA...
  • Page 5 P10 - Mach’s In System Programming (ISP)............ 69 5.1.8 MPC8260-ADS’s P16 - System Expansion Connector ........70 MPC8260-ADS Part List ..................76 Programmable Logic Equations ................87 5.3.1 U18 - BCSR & System Control ................ 89 5.3.2 U15 - SDRAM’s Latch-Mux ................109 MOTOROLA Contents...
  • Page 6 . P5 - COP / JTAG Connector - Interconnect Signals..........68 Table 5-6 . P10 - ISP Connector - Interconnect Signals ............69 Table 5-7 . P16 - System Expansion - Interconnect Signals ..........71 Table 5-8 . MPC8260-ADS Bill of Materials ................76 Table 5-9 . MPC8260-ADSL2C Part List ................82 MOTOROLA Tables...
  • Page 7 . SDRAM DIMM Connection Scheme..............40 Figure 4-3 . Local SDRAM Connection Scheme ..............44 Figure 4-4 . RS-232 Serial Port Connectors ................48 Figure 4-5 . Debug Station Connection Schemes..............55 Figure 4-6 . COP/JTAG Port Connector..................56 Figure 4-7 . ADS Power Scheme.....................57 MOTOROLA Illustrations...

  • Page 8: Chapter 1 General Information

    ) • PMC-SIERRA 5350 Long Form Data Sheet • PMC-SIERRA 5350 Errata Notice • PMC-SIERA 5350 Reference Design • LXT970A (by Level One) Data Sheet • LXT970 Demo Board User’s Guide Either on or off-board. MOTOROLA Chapter 1. General Information...

  • Page 9: Specifications

    4 MBytes, organized as 1 Meg X 32 bit. Operating temperature C - 30 C (room temperature) Storage temperature C to 85 Relative humidity 5% to 90% (non-condensing) Dimensions: Length 11.023" (280 mm) Width 6.417" (163 mm) Thickness 0.063" (1.6 mm) MPC8260 PowerQUICC II ADS User’s Manual MOTOROLA...

  • Page 10: Ads Features

    Reset Push - Button The DIMM is unbuffered from the 60X bus and therefore should consume as small capacitive drive power as possible. Hard reset is applied by depressing BOTH Soft Reset & ABORT buttons. MOTOROLA Chapter 1. General Information 1-10...
  • Page 11 Reverse / Over Voltage Protection for Power Inputs. 2V - 2.5V MPC8260 Internal Logic Operation, currently changeable. Software Option Switch provides 8 S/W options via BCSR. Unless a 12V programmable Flash SIMM is being used. 1-11 MPC8260 PowerQUICC II ADS User’s Manual MOTOROLA...

  • Page 12: Figure 1-1. Mpc8260-Ads Block Diagram

    DATA Transceivers & OPTIONAL Address Latches Flash SIMM. 60X Bus (buffered) 8 - 32MByte 32 - Bit MPC8260 3.3V<->5V JTAG Port SCC(1:2) Connector (16 pin) 3.3V 3.3V FCC2 Magnetics LXT970 FCC1 PM5350 3.3V<->5V Buffered System Bus MOTOROLA Chapter 1. General Information 1-12...

  • Page 13: Chapter 2 Hardware Preparation And Installation

    • MPC Internal Logic Supply Level (VDDL) Via TR1 • MPC8260’s MODCK(1:3). Determining Core’s and CPM’s PLLs multiplication factor via DS1. • SDRAM DIMM’s I C Slave Address via DS2. 2-13 MPC8260 PowerQUICC II ADS User’s Manual MOTOROLA...

  • Page 14: Figure 2-1. Mpc8260-Ads Top Side Part Location Diagram

    Figure 2-1. MPC8260-ADS Top Side Part Location diagram MOTOROLA Chapter 2. Hardware Preparation and Installation 2-14...

  • Page 15: Setting Vddl Supply Voltage Level

    Core’s PLLs. The levels on MODCK(1:3) lines is set using DS1, switches #1 - #3 . DS1 is shown in FIGURE 2-3 "DS1 Description" on page Note that on ENG boards it conflicts with the marking on the board. This document OVERRIDES. Switch #4 is reserved. 2-15 MPC8260 PowerQUICC II ADS User’s Manual MOTOROLA...

  • Page 16: Sdram Dimm I2C Slave Address Selection - Ds2

    SDRAM DIMM configuration EEPROM slave address for the convenience of the user. DS2 is shown in FIGURE 2-4 "DS2 Description" on page MOTOROLA Chapter 2. Hardware Preparation and Installation 2-16...

  • Page 17: Installation Instructions

    JTAG port. This configuration allows for extensive debugging using on-host de- bugger. The host is connected to the ADS by either ADI2COP card or by any other COP controller. 2-17 MPC8260 PowerQUICC II ADS User’s Manual MOTOROLA...

  • Page 18: Stand Alone Operation

    5V Power Supply 2.4.3 +5V Power Supply Connection The MPC8260-ADS requires +5 Vdc @ 5 A max, power supply for operation. Connect the +5V power supply to connector P19 as shown below: MOTOROLA Chapter 2. Hardware Preparation and Installation 2-18...

  • Page 19: P1: +12V Power Supply Connection

    MPC8260-ADS and the COP controller is by a 16 line flat cable, supplied with the COP controller board. FIGURE 2-9 "P1 - COP/JTAG Port Connector" below shows the pin configuration of the connector. Could be ADI2COP or any third party COP controller. 2-19 MPC8260 PowerQUICC II ADS User’s Manual MOTOROLA...

  • Page 20: Terminal To Mpc8260-Ads Rs-232 Connection

    10/100-Base-T port to the network is done by a standard cable, having two RJ45/ 8 jacks on its ends. The pinout of P2 is described in TABLE 5-2. "P2 - Ethernet Port Interconnect Signals" on page IBM-AT is a trademark of International Business Machines Inc. MOTOROLA Chapter 2. Hardware Preparation and Installation 2-20...

  • Page 21: Memory Installation

    DIMM matches those on the socket and then, the DIMM should be pressed evenly and firmly into its place, locking the side locks on itself. The SDRAM in- sertion is shown in FIGURE 2-12 "SDRAM DIMM Insertion" below: 2-21 MPC8260 PowerQUICC II ADS User’s Manual MOTOROLA...

  • Page 22: Figure 2-12. Sdram Dimm Insertion

    Figure 2-12. SDRAM DIMM Insertion RIGHT SIDE VIEW MOTOROLA Chapter 2. Hardware Preparation and Installation 2-22...

  • Page 23: Chapter 3 Operating Instructions

    The combination of the switches composing DS1, sets, during Power-On reset sequence, the MODCK(1:3) field for the MPC8260. DS1 is factory set to 1 - OFF, 2 - ON, 3 - OFF, 4 - OFF (X). 3-23 MPC8260 PowerQUICC II ADS User’s Manual MOTOROLA...

  • Page 24: Ds2 - Sdram Dimm Configuration Memory I2C Slave Address Switch

    DS3 is a 4-switch Dip-Switch. This switch is connected over SWOPT(0:2) lines which are available at BCSR2, S/W options may be manually selected, according to DS3 state. DS3 is factory set to all ON. MOTOROLA Chapter 3. Operating Instructions 3-24...

  • Page 25: J1 - Vpp Source Selector

    To support an optional cooling ventilator for the MPC8260, J3 a 0.1" 2 pin header connector (not assembled) is provided. In order to connect a ventilator to J3, either a 0.1" pitch header should be 3-25 MPC8260 PowerQUICC II ADS User’s Manual MOTOROLA...

  • Page 26: J4 - Iddh Measurement

    MPC8260- ADS. 3.2.13 Fast Ethernet RX Indicator - LD1 The green Ethernet Receive LED indicator blinks whenever the LXT970 is receiving data from one of the 10/100-Base-T port. MOTOROLA Chapter 3. Operating Instructions 3-26...

  • Page 27: Ethernet Tx Indicator - Ld2

    This red indication led has no dedicated function over the ADS. It is meant to provide additional visibility for program behavior. Its different color from LD11 provides additional information. It is controlled by BCSR0. 3-27 MPC8260 PowerQUICC II ADS User’s Manual MOTOROLA...

  • Page 28: Fast Ethernet Port Initially Enabled - Ld13

    SDRAM DIMM and Flash memory SIMM mounted on board and initializes the memory controller accordingly. The SDRAM and the Flash memory, respond to all types of memory access i.e., MOTOROLA Chapter 3. Operating Instructions 3-28...

  • Page 29: Table 3-1. Ads Memory Map

    The device appears repeatedly in multiples of its port-size (in bytes) X depth. E.g., BCSR0 appears at memory locations 4700000, 4700010, 4700020..., while BCSR1 appears at 4700004, 4700014, 4700024... and so on. 3-29 MPC8260 PowerQUICC II ADS User’s Manual MOTOROLA...

  • Page 30: Mpc8260 Register Programming

    The internal registers of the MPC must be programmed after Hard reset as described in the following paragraphs. The addresses and programming values are in Hexadecimal base. For more information on the following initializations, see the MPC8260 User’s Manual. MOTOROLA Chapter 3. Operating Instructions 3-30...

  • Page 31: System Initialization

    With L2 cache 3.4.2 Memory Controller Register Programming The memory controller on the MPC8260-ADS is initialized to 66 MHz operation. I.e., register pro- gramming is based on 66 MHZ timing calculation.. 3-31 MPC8260 PowerQUICC II ADS User’s Manual MOTOROLA...

  • Page 32: Table 3-4. Memory Controller Initialization For 66Mhz

    Base at 04000000, 32 bit port size, no parity, SDRAM machine 2 FFC00880 4 MByte block size,2 banks per device, row starts at A8, 10 row lines, internal bank interleaving allowed, normal AACK operation MOTOROLA Chapter 3. Operating Instructions 3-32...
  • Page 33 MPTPR All SDRAMs on board 3200 Divide Bus clock by 50 (decimal) With L2 cache. BNKSEL(0:2) are not connected for the Local Bus sdram. Use is done with Local bus address lines. 3-33 MPC8260 PowerQUICC II ADS User’s Manual MOTOROLA...

  • Page 34: Chapter 4 Functional Description

    To save on board area, this button is not a dedicated one, but is shared with the Soft-Reset button and the ABORT button - when both depressed, Hard Reset is generated. MOTOROLA Chapter 4. Functional Description 4-34...

  • Page 35: Hard Rest Configuration

    In general, the MPC8260 for which RSTCONF~ is asserted along with PORST~ asserted or in particular, the MPC8260 residing on the ADS. Although the MPC8260 as configuration master reads 8 configuration words, only the 1’st configuration word is influential. 4-35 MPC8260 PowerQUICC II ADS User’s Manual MOTOROLA...

  • Page 36: Manual Soft Reset

    In general, the MPC8260 asserts a reset line HARD or SOFT for a period 512 clock cycles after a reset source has been identified. A hard reset sequence is followed by a soft reset sequence. MOTOROLA Chapter 4. Functional Description...

  • Page 37: Local Interrupter

    Special care is taken to isolate and terminate the clock routes between the clock-distributor and on-board consumers, this to provide "clean" clock inputs for proper operation. Figure 4-1. Clock Generator Scheme MPC8260 CLOCK GEN. 66 MHz SKEW BUF. 4-37 MPC8260 PowerQUICC II ADS User’s Manual MOTOROLA...

  • Page 38: Bus Configuration

    If necessary. Required for Flash and BCSR An address which covered in a Chip-Select region, that controls a buffered device. To allow a configuration word stored in Flash memory become active. And off-board. See further. MOTOROLA Chapter 4. Functional Description 4-38...

  • Page 39: Synchronous Dram Dimm (60X Bus)

    The SDRAM’s timing is controlled by SDRAM Machine #1, (associated with 60X bus,) via its assigned Chip Select line (See TABLE 4-2. "ADS Chip Select Assignments" on page 39). The sdram connection scheme is shown in FIGURE 4-2 "SDRAM DIMM Connection Scheme" below. 4-39 MPC8260 PowerQUICC II ADS User’s Manual MOTOROLA...

  • Page 40: Figure 4-2. Sdram Dimm Connection Scheme

    PSDDQM(0:7) DQMB(0:7) D(0:63) DQ(0:63) 0 Ω Res. CLK(3:6) CLK(1:4) PSDAMUX I2CDAT I2CCLK SA(2:0) Serial EEPROM Slave Address Setting Switches. Optional Cache Support The SDRAM performance, is shown in TABLE 4-3. "SDRAM DIMM (84MHz) Performance MOTOROLA Chapter 4. Functional Description 4-40...

  • Page 41: Sdram Programming

    4 Word Burst Length Actually SDRAM’s A0 is connected to MPC8260’s A28 and so on... The SDRAM machine one of the MPC8260 needs to be initialized as well, this after BCSR2 is read 4-41 MPC8260 PowerQUICC II ADS User’s Manual MOTOROLA...

  • Page 42: Sdram Refresh

    If using the L2 cache, the MPC8260 needs to be programmed to 60x bus mode. This enables the In fact each SDRAM component is composed of 2 internal banks each having 2048 rows, but they are refreshed in parallel. MOTOROLA Chapter 4. Functional Description 4-42...

  • Page 43: Flash Programming Voltage

    Local Bus and is assigned to a CS line according to TABLE 4-2. "ADS Chip Select As well as all other slow static devices. I.e., initializations that follow the hard reset sequence at system boot. 4-43 MPC8260 PowerQUICC II ADS User’s Manual MOTOROLA...

  • Page 44: Table 4-6 . Local Bus Sdram Performance Figures - 66Mhz

    Not including arbitration overhead. Figure 4-3. Local SDRAM Connection Scheme LSDRAS LDCAS LSDWE LA18 LSDA10 LA(20:21) A(9:8) A(9:8) LA(22:29) A(7:0) A(7:0) CLK7 LSDDQM0 DQMU DQMU LSDDQM1 DQML DQML DQ(15:0) DQ(15:0) LCL_D(0:15) LSDDQM2 LSDDQM3 LD(16:31) MOTOROLA Chapter 4. Functional Description 4-44...

  • Page 45: Local Bus Sdram Programming

    60X bus protocol, allowing address pipelining In fact each SDRAM component is composed of 2 internal banks each having 2048 rows, but they are refreshed in parallel. I.e., residing on the same bus as the processor. 4-45 MPC8260 PowerQUICC II ADS User’s Manual MOTOROLA...

  • Page 46: Local Bus Sdram Refresh

    155 Mbps ATM UNI on FCC1 with Optical I/f, connected via UTOPIA I/F. 10/100-Base-T Port on FCC2, MII controlled. Dual RS232 port residing on SCC1 & SCC2. Only single level is allowed with the MPC8260. For minimum 8 Bus clock cycles. MOTOROLA Chapter 4. Functional Description 4-46...

  • Page 47: Atm Port

    When R87 is assembled and R86 is omitted, the transmit and receive fifo clocks are the same. When R87 is omitted and R86 is assembled, CLK11 would be on the ATM transmit fifo clock, while CLK12 would be on the receive fifo clock. 4-47 MPC8260 PowerQUICC II ADS User’s Manual MOTOROLA...

  • Page 48: Figure 4-4. Rs-232 Serial Port Connectors

    The following functions are controlled / monitored by the BCSR: L2 Cache Inhibit L2 Cache Flush L2 Cache Lock L2 Cache tag Clear. ATM Port Control which includes: Since there are only 3 RS232 transmitters in the device, DSR is connected to CD. MOTOROLA Chapter 4. Functional Description 4-48...

  • Page 49: Ports Signal Description

    This signal is connected to the L2 FLUSH signal of the MPC2605. This signal has no function in a ADS that does not have an L2 Cache installed. 4-49 MPC8260 PowerQUICC II ADS User’s Manual MOTOROLA...

  • Page 50: Bcsr0 - Board Control - Status Register 0

    The BCSR1 serves as a control register on the ADS. It is accessed at offset 4 from BCSR base address. It may be read or written at any time. BCSR1 gets its defaults upon Power-On reset. MOTOROLA Chapter 4. Functional Description...

  • Page 51: Bcsr2 - Board Control - Status Register - 2

    BCSR2 is a status register which is accessed at offset 8 from the BCSR base address. Its a Read- Only register which may be read at any time. BCSR2’s various fields are described in TABLE 4- 11. "BCSR2 Description" on page 4-51 MPC8260 PowerQUICC II ADS User’s Manual MOTOROLA...

  • Page 52: Table 4-11. Bcsr2 Description

    13. "Flash Presence Detect (4:1) Encoding" on page 53 There is additional bit to this field. See bit 24 in the same table. Table 4-12. Flash Presence Detect (7:5) Encoding FLASH_PD(7:5) FLASH DELAY [nsec] Not Supported 100/120 MOTOROLA Chapter 4. Functional Description 4-52...

  • Page 53: Table 4-13. Flash Presence Detect (4:1) Encoding

    SM73248XG2JHBG0 - 16 MByte (2 banks of 4 X 2M X 8) by Smart Modular Technology. 0010 SM73228XG1JHBG0 - 8 MByte (1 bank of 4 X 2M X 8) by Smart Modular Technology. 0011 - 1111 Not Supported 4-53 MPC8260 PowerQUICC II ADS User’s Manual MOTOROLA...

  • Page 54: Table 4-14. Extool(0:3) Assignment

    Revision Number (0:3) ADS Revision [Hex] ENG (Engineering) PILOT 3 - F Reserved Table 4-17. L2 Cache Size Encoding L2CSIZE(0:1) L2 Cache Size ’00’ No L2 Cache ’01’ Reserved ’10’ 512 KBytes ’11’ Reserved MOTOROLA Chapter 4. Functional Description 4-54...

  • Page 55: Bcsr3 - Board Control - Status Register 3

    (P5) is provided on the ADS, carrying the COP/JTAG signals as well as additional signals aiding in system debug. The pinout of this connector, is a general Motorola recommendation for including a COP/JTAG port in a design. The pinout of the COP/JTAG connector is shown in FIGURE 4-6 "COP/JTAG Port Connector"...

  • Page 56: Power

    3) VCCSYN (CPM PLL) 4) VCCSYN1 (Core PLL) and there are 4 power buses on the ADS: 1) VCC (5V) bus 2) V3.3 (3.3V) bus 3) VDDL (2V-2.5V) bus 4) VPP (5V / 12V) bus MOTOROLA Chapter 4. Functional Description 4-56...

  • Page 57: Bus

    The 5V bus is connected to an external power connector via a fuse (5A). To protect against reverse-voltage or over-voltage being applied to the 5V inputs a set of high- 4-57 MPC8260 PowerQUICC II ADS User’s Manual MOTOROLA...

  • Page 58: Bus

    If either the Flash SIMM is 5V programmable or it is 12V programmable but need not be pro- grammed - the 12V supply input connector of the ADS - P1, may be left un-connected. If necessary. MOTOROLA Chapter 4. Functional Description 4-58...

  • Page 59: Chapter 5 Support Information

    Twisted-Pair Transmit Data positive output from the MPC8260-ADS. TPTX~ Twisted-Pair Transmit Data negative output from the MPC8260-ADS. TPRX Twisted-Pair Receive Data positive input to the MPC8260-ADS. N.C. Not connected, Bob Smith terminated on the MPC8260-ADS. 5-59 MPC8260 PowerQUICC II ADS User’s Manual MOTOROLA...

  • Page 60: Pa3, Pb3 - Rs232 Ports' Connectors

    When this port is disabled, this signal may be used to any available alternate function for PD30. PD29 I/O, T.S MPC8260’s Port D 29 line. Parallel I/O or CPM dedicated line.May be used for any of it’s available functions. MOTOROLA Chapter 5. Support Information 5-60...
  • Page 61 C device, as long as the I C addresses of the SDRAM DIMM and the external device’s - do not conflict. See 2.4.8.2 "SDRAM DIMM Installation" on page 21 "Synchronous Dram DIMM (60X Bus)" on page 39 5-61 MPC8260 PowerQUICC II ADS User’s Manual MOTOROLA...
  • Page 62 PM5350’s ATMRXD(7:0) lines. When negated while ATMRFCLK goes high data ATMRXD(7:0) is invalid, however driven. When the ATM port is disabled, this line may be used for any available function for PA28. MOTOROLA Chapter 5. Support Information 5-62...
  • Page 63 ATMRFCLK When the ATM port is disabled, these lines are tristated and may ATMRXD5 (PA15) be used for any available respective function. ATMRXD4 (PA14) ATMRXD3 (PA13) ATMRXD2 (PA11) ATMRXD1 (PA11) ATMRXD0 (PA10) 5-63 MPC8260 PowerQUICC II ADS User’s Manual MOTOROLA...
  • Page 64 Collision state over the line. When the LXT970 is in Full-Duplex mode, this line is inactive. When the Ethernet port is disabled, this line is tristated and may be used for any available function of the PB27. MOTOROLA Chapter 5. Support Information 5-64...
  • Page 65 MPC8260’s Port B (17:4) Parallel I/O lines. May be used to any of their available functions. PB16 PB15 PB14 PB13 PB12 PB11 PB10 Digital Ground. Connected to main GND plane of the ADS. 5-65 MPC8260 PowerQUICC II ADS User’s Manual MOTOROLA...
  • Page 66 This line is simply a PI/O input line to the MPC8260. When RS232 Port 1 is disabled, this line is tristated and may be used for any available function of PC14. MOTOROLA Chapter 5. Support Information 5-66...

  • Page 67: P5 - Cop / Jtag Port Connector

    5.1.5 P5 - COP / JTAG Port Connector P5 is a Motorola standard COP / JTAG connector for the 60X processors family. It is a 16 pin 90 protected header connector with locks. The pinout of P5 is shown in TABLE 5-5.

  • Page 68: Table 5-5. P5 - Cop / Jtag Connector - Interconnect Signals

    When driven by an external tool, MUST be driven with an Open Drain gate. Failure to do so may result in permanent damage to the MPC8260 and / or to ADS logic. N.C. Not Connected. MOTOROLA Chapter 5. Support Information 5-68...

  • Page 69: P6, P7, P8, P9, P11, P12, P13, P14 & P15 - Logic Analyzer Connectors

    5V power supply bus. ISPTDO ISP Transmit Data Output. This the prog. logic’s JTAG serial data output driven by Falling edge of TCK. Digital GND. Main GND plane. N.C. Not Connected. N.C. Not Connected. 5-69 MPC8260 PowerQUICC II ADS User’s Manual MOTOROLA...

  • Page 70: Mpc8260-Ads's P16 - System Expansion Connector

    P4. This connector contains 16 bit (lower PPC bus) address lines, 16 bit (higher PPC bus) Data lines plus useful GPCM and UPM control lines. The pinout of P16 is shown in MOTOROLA Chapter 5. Support Information...

  • Page 71: Table 5-7. P16 - System Expansion - Interconnect Signals

    The amount of current TABLE 4- allowed to be drawn from this power bus is found in "Off-board Application Maximum Current Consumption" on page 57 N.C. Not Connected. 5-71 MPC8260 PowerQUICC II ADS User’s Manual MOTOROLA...
  • Page 72 MPC8260-ADS, this, to provide 3.3V power where necessary for external tool connected. The amount of current TABLE 4- allowed to be drawn from this power bus is found in "Off-board Application Maximum Current Consumption" on page 57 N.C. Not Connected MOTOROLA Chapter 5. Support Information 5-72...
  • Page 73 ATM UNI’s interrupt line and therefore, when driven by an external tool, MUST be driven with an Open Drain gate. Failure to do so may result in permanent damage to the MPC8260 or to ADS logic. 5-73 MPC8260 PowerQUICC II ADS User’s Manual MOTOROLA...
  • Page 74 EXPWE0~ controls EXPD(0:7) while EXPWE1~ controls EXPD(8:15). These lines may also function as UPM controlled Byte Select Lines, which allow control over almost any type of memory device. MOTOROLA Chapter 5. Support Information 5-74...
  • Page 75 Expansion Control Line 0. This line is a buffered version of MPC8260’s BCTL0 (Bus Control Line 0) which serves as R~/W, provided for expansion board’s use. Digital Ground. Connected to main GND plane of the ADS. MS Bit. 5-75 MPC8260 PowerQUICC II ADS User’s Manual MOTOROLA...

  • Page 76: Mpc8260-Ads Part List

    SMD 1206 Ceramic C150 Capacitor 1µF, 20V, 10%, SMD SIEMENS B45196H5105K109 SIze B, Tantalum C170 C171 Capacitor 10pF, 50V, 10%, SMD SIEMENS 1206, Ceramic C203 Capacitor 0.001µF, 2 KV, 10%, 1210B102K202NT SMD SIze 1210, Ceramic MOTOROLA Chapter 5. Support Information 5-76...
  • Page 77 Manufacturer Part # C204 C205 Capacitor 0.1µF, X7R, 500V, 20%, JOHANSON 501S43W104MV4E SMD SIze 1812, Ceramic DIELECTRIC D1 D5 Diode Pair, common cathode Motorola MBRD620CT Zener Diode, 5V SMD Motorola 1SMC5.0AT3 Diode SMD Motorola LL4004G Zener Diode, 12V SMD Motorola...
  • Page 78 DRALORIK D25-051J-S Resistor 75 Ω, 5%, SMD 0603, R73 R77 R80 DRALORIK D11 075RFCS 0.1W Resistor 0 Ω, SMD 1206, 1/4W RODERSTEIN D25 000RFCS Resistor 20 Ω, 5%, SMD 1206, 1/ DRALORIK D25 020RFCS MOTOROLA Chapter 5. Support Information 5-78...
  • Page 79 RN13 RN15 RN16 RN19 RN23 DALE CRA06S0803220JR RN60 resistors, 8 pin. Resistor Network 0 Ω, 4 resistors, RN14 RN18 RN22 DALE CRA06S0803 000 RT 8 pin. SPDT, push button, RED, Sealed C & K KS12R22-CQE 5-79 MPC8260 PowerQUICC II ADS User’s Manual MOTOROLA...
  • Page 80 BOURNS 3362P-1-102 Fiber Optic I/F Module, 1300 nm HFBR 5205 wavelength, 2 Km Range U2 U5 3.3V Powered, Single Supply, Motorola MC145583V RS232 Transceiver (3 Tx, 5 Rx). 10/100 Base-T Filter network HALO TG22-3506ND Saturn User Network I/F (S/UNI) PMC-Sierra Inc.
  • Page 81 Table 5-8. MPC8260-ADS Bill of Materials Reference Designation Part Description Manufacturer Part # U21 U26 U28 Low Voltage, CMOS, 5V Tolerant Motorola MC74LCX16244DT 16 bit buffer, with OEs. 48 pin Plastic TSSOP, Case 1201-01 8 MByte Flash SIMM, 95 nsec Smart Modular SM73228XG1JHBG0...

  • Page 82: Table 5-9. Mpc8260-Adsl2C Part List

    SMD 1206 Ceramic C150 Capacitor 1µF, 20V, 10%, SMD SIEMENS B45196H5105K109 SIze B, Tantalum C170 C171 Capacitor 10pF, 50V, 10%, SMD SIEMENS 1206, Ceramic C203 Capacitor 0.001µF, 2 KV, 10%, 1210B102K202NT SMD SIze 1210, Ceramic MOTOROLA Chapter 5. Support Information 5-82...
  • Page 83 Manufacturer Part # C204 C205 Capacitor 0.1µF, X7R, 500V, 20%, JOHANSON 501S43W104MV4E SMD SIze 1812, Ceramic DIELECTRIC D1 D5 Diode Pair, common cathode Motorola MBRD620CT Zener Diode, 5V SMD Motorola 1SMC5.0AT3 Diode SMD Motorola LL4004G Zener Diode, 12V SMD Motorola...
  • Page 84 DRALORIK D25-051J-S Resistor 75 Ω, 5%, SMD 0603, R73 R77 R80 DRALORIK D11 075RFCS 0.1W Resistor 0 Ω, SMD 1206, 1/4W RODERSTEIN D25 000RFCS Resistor 20 Ω, 5%, SMD 1206, 1/ DRALORIK D25 020RFCS MOTOROLA Chapter 5. Support Information 5-84...
  • Page 85 Resistor Network 22 Ω, 5%, 4 RN13 RN15 RN16 RN19 RN23 DALE CRA06S0803220JR RN60 resistors, 8 pin. SPDT, push button, RED, Sealed C & K KS12R22-CQE SPDT, push button, BLACK, C & K KS12R23-CQE Sealed 5-85 MPC8260 PowerQUICC II ADS User’s Manual MOTOROLA...
  • Page 86 BOURNS 3362P-1-102 Fiber Optic I/F Module, 1300 nm HFBR 5205 wavelength, 2 Km Range U2 U5 3.3V Powered, Single Supply, Motorola MC145583V RS232 Transceiver (3 Tx, 5 Rx). 10/100 Base-T Filter network HALO TG22-3506ND Saturn User Network I/F (S/UNI) PMC-Sierra Inc.

  • Page 87: Programmable Logic Equations

    Table 5-9. MPC8260-ADSL2C Part List Reference Designation Part Description Manufacturer Part # U21 U26 U28 Low Voltage, CMOS, 5V Tolerant Motorola MC74LCX16244DT 16 bit buffer, with OEs. 48 pin Plastic TSSOP, Case 1201-01 8 MByte Flash SIMM, 95 nsec Smart Modular SM73228XG1JHBG0...
  • Page 88 U15, serving as Latch-Mux for the SDRAM DIMM. Use is done by MACH211SP-7VC by AMD. MOTOROLA Chapter 5. Support Information 5-88...

  • Page 89: U18 - Bcsr & System Control

    71 istype 'reg,buffer' ; " local bus sdram enable SignaLamp0_B 58 istype 'reg,buffer' ; " status lamp 0 for misc s/ w visual SignaLamp1_B 70 istype 'reg,buffer' ; " status lamp 1 for misc s/ 5-89 MPC8260 PowerQUICC II ADS User’s Manual MOTOROLA...
  • Page 90 37 istype 'com' ; " Flash bank4 chip-select "****************************************************************************** "* PMI5346 ATM UNI Associated Pins. "****************************************************************************** AtmUniCsIn_B AtmUniCsOut_B 11 istype 'com' ; " remove if short of pins "****************************************************************************** "* Reset & Interrupt Logic Pins. "****************************************************************************** PORIn_B MOTOROLA Chapter 5. Support Information 5-90...
  • Page 91 44; " comm tool cs line 2. ToolDataBufEn_B 93 istype 'com,invert' ; " tool data buffer enable "****************************************************************************** "* Auxiliary Pins. "****************************************************************************** "* System Hard Reset Configuration. "****************************************************************************** DataOeNODE istype 'com' ;" data bus output enable on read. 5-91 MPC8260 PowerQUICC II ADS User’s Manual MOTOROLA...
  • Page 92 NODE istype 'com' ; " terminal count for that counter "****************************************************************************** "* Power On Reset "****************************************************************************** S_PORIn_B NODE istype 'reg,buffer' ; " synced pon reset. "****************************************************************************** "* Misceleneous. "****************************************************************************** KeepPinsConnected node istype 'com' ; "****************************************************************************** MOTOROLA Chapter 5. Support Information 5-92...
  • Page 93 ContReg = [L2Inh_B, L2Flush_B, L2Lock_B, L2Clear_B, SignaLamp0_B, SignaLamp1_B, AtmEn_B, AtmRst_B, FEthEn_B, FEthRst_B, RS232En1_B, RS232En2_B] ; ReadBcsr0 = [0, L2Inh_B, L2Flush_B, L2Lock_B, L2Clear_B, SignaLamp0_B, SignaLamp1_B] ; ReadBcsr1 = [0, AtmEn_B, AtmRst_B.fb, FEthEn_B, FEthRst_B.fb, 5-93 MPC8260 PowerQUICC II ADS User’s Manual MOTOROLA...
  • Page 94 L2Flush_B, L2Lock_B, L2Clear_B, SignaLamp0_B, SignaLamp1_B, AtmEn_B, AtmRst_B, FEthEn_B, FEthRst_B, RS232En1_B, RS232En2_B] ; Bcsr0 = [L2Inh_B," for simulation L2Flush_B, L2Lock_B, L2Clear_B, SignaLamp0_B, SignaLamp1_B] ; Bcsr1 = [AtmEn_B," for simulation AtmRst_B, FEthEn_B, FEthRst_B, RS232En1_B, RS232En2_B] ; MOTOROLA Chapter 5. Support Information 5-94...
  • Page 95 VGR_READ_BCSR_0 = (!BrdContRegCs_B & !R_B_W & !A28 & !A29) ; VGR_READ_BCSR_1 = (!BrdContRegCs_B & !R_B_W & !A28 & A29) ; VGR_READ_BCSR_2 = (!BrdContRegCs_B & !R_B_W & A28 & !A29) ; VGR_READ_BCSR_3 = (!BrdContRegCs_B & !R_B_W & A28 & A29) ; 5-95 MPC8260 PowerQUICC II ADS User’s Manual MOTOROLA...
  • Page 96 L2CACHE_CLEAR_DATA_BIT = [D29] ; SIGNAL_LAMP0_DATA_BIT = [D30] ; SIGNAL_LAMP1_DATA_BIT = [D31] ; "****************************************************************************** "****************************************************************************** "* BCSR 1 definitions. "****************************************************************************** "****************************************************************************** ATM_ENABLED = 0 ; ATM_RESET_ACTIVE = 0 ; FETH_ENABLED = 0 ; FETH_RESET_ACTIVE = 0 ; MOTOROLA Chapter 5. Support Information 5-96...
  • Page 97 " 2 X 8 MByte banks SM73288XU4 = (F_PD == 0) ; " 4 X 8 MByte banks FLASH_BANK1 = ( SM73228XU1 # (SM73248XU2 & !A8) # (SM73288XU4 & !A7 & !A8) ) ; 5-97 MPC8260 PowerQUICC II ADS User’s Manual MOTOROLA...
  • Page 98 !DVal_B & !AtmUniCsIn_B & R_B_W # " atm uni write !DVal_B & !ToolCs1_B & R_B_W #" tool 1 write !DVal_B & !ToolCs2_B & R_B_W #" tool 2 write !DVal_B & !FlashCs_B & R_B_W) ; " flash write "****************************************************************************** MOTOROLA Chapter 5. Support Information 5-98...
  • Page 99 (PON_RESET & (L2CACHE_INH_PON_DEFAULT == L2CACHE_INHIBITED)) ) then L2CACHE_INHIBITED else !L2CACHE_INHIBITED ; "****************************************************************************** state_diagram L2Flush_B state L2CACHE_FLUSHED: if (VGR_WRITE_BCSR_0 & (L2CACHE_FLUSH_DATA_BIT.pin == !L2CACHE_FLUSHED) & (!PON_RESET # (L2CACHE_FLUSH_PON_DEFAULT != L2CACHE_FLUSHED)) # (PON_RESET & (L2CACHE_FLUSH_PON_DEFAULT == !L2CACHE_FLUSHED)) ) then !L2CACHE_FLUSHED 5-99 MPC8260 PowerQUICC II ADS User’s Manual MOTOROLA...
  • Page 100 L2CACHE_CLEARED: if (VGR_WRITE_BCSR_0 & (L2CACHE_CLEAR_DATA_BIT.pin == !L2CACHE_CLEARED) & (!PON_RESET # (L2CACHE_CLEAR_PON_DEFAULT != L2CACHE_CLEARED)) # (PON_RESET & (L2CACHE_CLEAR_PON_DEFAULT == !L2CACHE_CLEARED)) ) then !L2CACHE_CLEARED else L2CACHE_CLEARED ; state !L2CACHE_CLEARED: if (VGR_WRITE_BCSR_0 & (L2CACHE_CLEAR_DATA_BIT.pin == L2CACHE_CLEARED) & MOTOROLA Chapter 5. Support Information 5-100...
  • Page 101 (PON_RESET & (SIGNAL_LAMP1_PON_DEFAULT == !SIGNAL_LAMP_ON)) ) then !SIGNAL_LAMP_ON else SIGNAL_LAMP_ON ; state !SIGNAL_LAMP_ON: if (VGR_WRITE_BCSR_0 & (SIGNAL_LAMP1_DATA_BIT.pin == SIGNAL_LAMP_ON) & (!PON_RESET # (SIGNAL_LAMP1_PON_DEFAULT != !SIGNAL_LAMP_ON)) # (PON_RESET & (SIGNAL_LAMP1_PON_DEFAULT == SIGNAL_LAMP_ON)) ) then SIGNAL_LAMP_ON else !SIGNAL_LAMP_ON ; 5-101 MPC8260 PowerQUICC II ADS User’s Manual MOTOROLA...
  • Page 102 (PON_RESET & (ATM_RESET_PON_DEFAULT == !ATM_RESET_ACTIVE)) ) then !ATM_RESET_ACTIVE else ATM_RESET_ACTIVE ; state !ATM_RESET_ACTIVE: if (VGR_WRITE_BCSR_1 & (ATM_RESET_DATA_BIT.pin == ATM_RESET_ACTIVE) & (!PON_RESET # (ATM_RESET_PON_DEFAULT != !ATM_RESET_ACTIVE)) # (PON_RESET & (ATM_RESET_PON_DEFAULT == ATM_RESET_ACTIVE)) ) then ATM_RESET_ACTIVE else !ATM_RESET_ACTIVE ; "****************************************************************************** state_diagram FEthEn_B MOTOROLA Chapter 5. Support Information 5-102...
  • Page 103 (PON_RESET & (FETH_RESET_PON_DEFAULT == FETH_RESET_ACTIVE)) ) then FETH_RESET_ACTIVE else !FETH_RESET_ACTIVE ; "****************************************************************************** state_diagram RS232En1_B state RS232_1_ENABLE: if (VGR_WRITE_BCSR_1 & (RS232_1_ENABLE_DATA_BIT.pin == !RS232_1_ENABLE) & (!PON_RESET # (RS232_1_ENABLE_PON_DEFAULT != RS232_1_ENABLE)) # (PON_RESET & (RS232_1_ENABLE_PON_DEFAULT == !RS232_1_ENABLE)) ) then !RS232_1_ENABLE 5-103 MPC8260 PowerQUICC II ADS User’s Manual MOTOROLA...
  • Page 104 (PON_RESET & (RS232_2_ENABLE_PON_DEFAULT == RS232_2_ENABLE)) ) then RS232_2_ENABLE else !RS232_2_ENABLE ; "****************************************************************************** "****************************************************************************** " External Read Registers' Chip-Selects "****************************************************************************** "****************************************************************************** equations Bcsr2Cs_B.oe = H ; !Bcsr2Cs_B = VGR_READ_BCSR_2 ; "****************************************************************************** "****************************************************************************** "* Read Registers. MOTOROLA Chapter 5. Support Information 5-104...
  • Page 105 SoftResetEn = RstDeb1.fb & !AbrDeb1.fb ;" only reset button depressed TransRst.oe = 3 ;" transceivers' reset, always enabled. !AtmRstOut_B = !AtmRst_B.fb # !HardReset_B ; !FEthRstOut_B = !FEthRst_B.fb # !HardReset_B ; "****************************************************************************** "* Hard reset configuration 5-105 MPC8260 PowerQUICC II ADS User’s Manual MOTOROLA...
  • Page 106 DataBufEn_B.oe = H ; !DataBufEn_B = ( !FlashCs_B " covers also hard reset config !BrdContRegCs_B # !AtmUniCsIn_B # !ToolCs1_B # !ToolCs2_B) & (!BUFFER_HOLD_OFF) ToolDataBufEn_B.oe = H ; !ToolDataBufEn_B = (!ToolCs1_B # !ToolCs2_B) & (!BUFFER_HOLD_OFF) MOTOROLA Chapter 5. Support Information 5-106...
  • Page 107 FlashCsOut.oe = ^hf ; !FlashCs1_B = !FlashCs_B & FLASH_BANK1 !FlashCs2_B = !FlashCs_B & FLASH_BANK2 !FlashCs3_B = !FlashCs_B & FLASH_BANK3 !FlashCs4_B = !FlashCs_B & FLASH_BANK4 "****************************************************************************** "* ATM UNI Chip Select "****************************************************************************** 5-107 MPC8260 PowerQUICC II ADS User’s Manual MOTOROLA...
  • Page 108 AtmUniCsOut_B.oe = H ; !AtmUniCsOut_B = !AtmUniCsIn_B ; "****************************************************************************** "* Power On Reset "****************************************************************************** equations S_PORIn_B.clk = SYSCLK ; S_PORIn_B := PORIn_B ; "****************************************************************************** "* Auxiliary functions "****************************************************************************** equations KeepPinsConnected = TEA_B ; MOTOROLA Chapter 5. Support Information 5-108...

  • Page 109: U15 - Sdram's Latch-Mux

    "* Pins declaration. "****************************************************************************** "* Control pins "****************************************************************************** Ale_B AleIn AleOut_B 25 istype 'com' ; " inverted AleIn, connected " externaly to Ale_B R_C_B "****************************************************************************** "* Address Input lines "****************************************************************************** " row " col 5-109 MPC8260 PowerQUICC II ADS User’s Manual MOTOROLA...
  • Page 110 NODE istype 'reg_D,buffer' ; LA12 NODE istype 'reg_D,buffer' ; LA13 NODE istype 'reg_D,buffer' ; LA14 NODE istype 'reg_D,buffer' ; LA15 NODE istype 'reg_D,buffer' ; LA16 NODE istype 'reg_D,buffer' ; LA17 NODE istype 'reg_D,buffer' ; MOTOROLA Chapter 5. Support Information 5-110...
  • Page 111 LAdd = [LA10..LA28] ; RowAdd = [LA10..LA19] ; ColAdd = [LA10,LA20..LA28] ; SDRAMAdd = [SDRAMA9..SDRAMA0] ; ROW = (R_C_B == 1) ; COL = !ROW ; "****************************************************************************** "* Equations, state diagrams. "****************************************************************************** "****************************************************************************** 5-111 MPC8260 PowerQUICC II ADS User’s Manual MOTOROLA...
  • Page 112 LAdd.le = Ale_B ; LAdd.d = Add ; " latching the address "****************************************************************************** "****************************************************************************** "* Output Mux "****************************************************************************** "****************************************************************************** equations SDRAMAdd.oe = ^h3ff ; "always enabled when (ROW) then SDRAMAdd = RowAdd.q else SDRAMAdd = ColAdd.q ; MOTOROLA Chapter 5. Support Information 5-112...