Reset 0000_0000_0000_0000; Field - Motorola PowerQUICC II MPC8280 Series Reference Manual

31

Field

Reset
R/W
Addr
15
Field
Reset
R/W
Addr
Figure 9-79. Messaging Unit Control Register (MUCR)
Table 9-64 describes MUCR fields.
Bits Name Access
31–6 — R
5–1 CQS RW
0 CQE RW
9.12.3.4.8 Queue Base Address Register (QBAR)
This register specifies the beginning of the circular queue structure in local memory. The
following QBAR should be accessed only from the 60x bus and only in agent mode.
Accesses while in host mode or from the PCI bus have undefined results.
MOTOROLA
Freescale Semiconductor, Inc.
0000_0000_0000_0002
—
0000_0000_0000_0000
Table 9-64. MUCR Field Descriptions
Reserved, should be cleared.
Circular queue size. CQS refers to each individual queue, not the total size of all four
queues together.
00001 4K entries (16 Kbytes)
00010 8K entries (32 Kbytes)
00100 16K entries (64 Kbytes)
01000 32K entries (128 Kbytes)
10000 64K entries (256 Kbytes)
All others reserved.
Circular queue enable. When set will allow PCI masters to access the inbound and
outbound queue ports. Writes are ignored and reads will return 0xFFFF_FFFF when
this bit is cleared. Normally, this bit is set only if software has initialized all pointers and
configuration registers.
Chapter 9. PCI Bridge
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—
R/W
0x104E6
6 5
R/W
0x104E4
Description
Message Unit (I O)
2
16
1 0
CQS CQE
9-89