Reset 0000_0000_0000_0000; R/W R/W; Addr - Motorola PowerQUICC II MPC8280 Series Reference Manual

DMA Controller
Table 9-68 describes DMACDARx fields.
Bits Name
31–5 CDA
4 SNEN
3 EOSIE
2–0 —
9.13.1.6.4 DMA Source Address Registers 0–3 (DMASARx)
The source address register, shown in Figure 9-85, indicates the address where the DMA
controller will be reading data from. This address can be in either PCI memory or 60x
memory. The software has to ensure that this is a valid memory address.
The choice between PCI or 60x is done according to the following rule: If the address hits
one of the PCI outbound windows, then the source data is read from the PCI memory.
Otherwise, it is read from the 60x memory. Refer to Figure 9-13.
31
Field
Reset
R/W

Addr

0x10512(DMASAR0); 0x10592 (DMASAR1); 0x10612 (DMASAR2); 0x10692 (DMASAR3)
15
Field
Reset
R/W
Addr 0x10510 (DMASAR0); 0x10590 (DMASAR1); 0x10610 (DMASAR2); 0x10690 (DMASAR3)
Figure 9-85. DMA Source Address Registers 0–3 (DMASARx)
Table 9-69 describes DMASARx fields.
Bit Name
31–0 SA
9-98
Freescale Semiconductor, Inc.
Table 9-68. DMACDARx Field Descriptions
Current descriptor address. Contains the current descriptor address of the segment
descriptor in memory. It must be aligned on an 8-word boundary.
Snoop enable. When set will allow snooping on DMA transactions.
End-of-segment interrupt enable. When set will generate an interrupt if the current DMA
transfer for the current descriptor is finished.
Reserved, should be cleared.
0000_0000_0000_0000
0000_0000_0000_0000
Table 9-69. DMASARx Field Descriptions
Source address of DMA transfer. The content is updated after every DMA read operation.
MPC8280 PowerQUICC II Family Reference Manual
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Description
SA
R/W
SA
R/W
Description
16
0
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