Motorola PowerQUICC II MPC8280 Series Reference Manual page 423

Table 9-72 describes DMANDARx fields.
Bit Name
31–5 NDA
4 NDSNEN
3 NDEOSIE
2–1 —
0 EOTD
9.13.2 DMA Segment Descriptors
DMA segment descriptors contain the source and destination addresses of the data
segment, the segment byte count, and a link to the next descriptor. Segment descriptors are
built on cache-line (32-byte) boundaries in either 60x or PCI memory and are linked
together into chains using the next-descriptor-address field.
Table 9-73. DMA Segment Descriptor Fields
Descriptor Field
Source address Contains the source address of the DMA transfer. After the DMA controller reads the
descriptor from memory, this field will be loaded into the source address register. For the bit
definition, refer to Section 9.13.1.6.4, "DMA Source Address Registers 0–3 (DMASARx)."
Destination address Contains the destination address of the DMA transfer. After the DMA controller reads the
descriptor from memory, this field will be loaded into the destination address register. For the
bit definition, refer to Section 9.13.1.6.5, "DMA Destination Address Registers 0–3
(DMADARx)."
Next descriptor address Points to the next descriptor in memory. After the DMA controller reads the descriptor from
memory, this field will be loaded into the next descriptor address register. For the bit definition,
refer to Section 9.13.1.6.7, "DMA Next Descriptor Address Registers 0–3 (DMANDARx)."
Byte count Contains the number of bytes to transfer. After the DMA controller reads the descriptor from
memory, this field will be loaded into the byte count register. For the bit definition, refer to
Section 9.13.1.6.6, "DMA Byte Count Registers 0–3 (DMABCRx)."
Application software initializes the current descriptor address register (DMACDARx) to
point to the first descriptor in the chain. For each descriptor in the chain, the DMA
controller starts a new DMA transfer with the control parameters specified by the
descriptor. The DMA controller traverses the descriptor chain until reaching the last
descriptor (with its EOTD bit set).
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Freescale Semiconductor, Inc.
Table 9-72. DMANDARx Field Descriptions
Next descriptor address. Contains the next descriptor address of the segment
descriptor in memory. It must be aligned on an 8-word (32-byte) boundary.
Next descriptor snoop enable. When set will allow snooping on DMA
transactions.
Next descriptor end-of-segment interrupt enable. When set will generate an
interrupt at the end of this DMA transfer.
Reserved, should be cleared.
End-of-transfer descriptor. When set indicates that this descriptor is the last one
to be executed.
Chapter 9. PCI Bridge
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Description
Description
DMA Controller
9-101