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Motorola DragonBall MC9328MX1 Reference Manual

Motorola DragonBall MC9328MX1 Reference Manual (968 pages)

Integrated Portable System Processor  
Brand: Motorola | Category: Processor | Size: 15.56 MB
Table of contents
Table Of Contents3................................................................................................................................................................
About This Book51................................................................................................................................................................
Document Revision History54................................................................................................................................................................
Block Diagram57................................................................................................................................................................
Features58................................................................................................................................................................
Figure 1-1 Mc9328mx1 Functional Block Diagram58................................................................................................................................................................
Arm920t Microprocessor Core59................................................................................................................................................................
Ahb To Ip Bus Interfaces (aipis)59................................................................................................................................................................
External Interface Module (eim)60................................................................................................................................................................
Sdram Controller (sdramc)60................................................................................................................................................................
Clock Generation Module (cgm) And Power Control Module60................................................................................................................................................................
Two Serial Peripheral Interfaces (spi)61................................................................................................................................................................
Two General-purpose 32-bit Counters/timers61................................................................................................................................................................
Watchdog Timer61................................................................................................................................................................
Real-time Clock/sampling Timer (rtc)62................................................................................................................................................................
Lcd Controller (lcdc)62................................................................................................................................................................
Pulse-width Modulation (pwm) Module62................................................................................................................................................................
Universal Serial Bus (usb) Device63................................................................................................................................................................
Multimedia Card And Secure Digital (mmc/sd) Host Controller63................................................................................................................................................................
Table 1-1 Endpoint Configurations63................................................................................................................................................................
Memory Stick® Host Controller (mshc)64................................................................................................................................................................
Smartcard Interface Module (sim)64................................................................................................................................................................
Direct Memory Access Controller (dmac)64................................................................................................................................................................
Synchronous Serial Interface And Inter-ic Sound (ssi/i 2 S) Module65................................................................................................................................................................
Video Port65................................................................................................................................................................
General-purpose I/o (gpio) Ports65................................................................................................................................................................
Bootstrap Mode65................................................................................................................................................................
Analog Signal Processing (asp) Module66................................................................................................................................................................
Bluetooth Accelerator (bta)66................................................................................................................................................................
Multimedia Accelerator (mma)66................................................................................................................................................................
Power Management Features66................................................................................................................................................................
Operating Voltage Range67................................................................................................................................................................
Packaging67................................................................................................................................................................
Signal Descriptions69................................................................................................................................................................
Table 2-1 Mc9328mx1 Signal Descriptions69................................................................................................................................................................
I/o Pads Power Supply And Signal Multiplexing Scheme76................................................................................................................................................................
Table 2-2 Mc9328mx1 Signal Multiplexing Scheme77................................................................................................................................................................
Memory Space87................................................................................................................................................................
Memory Map87................................................................................................................................................................
Figure 3-1 Mc9328mx1 Mcu Physical Memory Map (4 Gbyte)88................................................................................................................................................................
Table 3-1 Mcu Memory Space (physical Addresses)89................................................................................................................................................................
On-chip Mcu Memory91................................................................................................................................................................
Internal Register Space91................................................................................................................................................................
External Memory91................................................................................................................................................................
Double Map Image91................................................................................................................................................................
Internal Registers92................................................................................................................................................................
Table 3-2 Mc9328mx1 Internal Registers Sorted By Address92................................................................................................................................................................
Introduction117................................................................................................................................................................
Arm920t Macrocell118................................................................................................................................................................
Caches118................................................................................................................................................................
Figure 4-1 Arm920t Core Functional Block Diagram118................................................................................................................................................................
Cache Lock-down119................................................................................................................................................................
Write Buffer119................................................................................................................................................................
Patag Ram119................................................................................................................................................................
Mmus119................................................................................................................................................................
System Controller119................................................................................................................................................................
Control Coprocessor (cp15)120................................................................................................................................................................
Armv4t Architecture120................................................................................................................................................................
Registers120................................................................................................................................................................
Modes And Exception Handling120................................................................................................................................................................
Status Registers120................................................................................................................................................................
Exception Types121................................................................................................................................................................
Conditional Execution121................................................................................................................................................................
Four Classes Of Instructions121................................................................................................................................................................
Data Processing Instructions121................................................................................................................................................................
Load And Store Instructions122................................................................................................................................................................
Addressing Modes122................................................................................................................................................................
Block Transfers122................................................................................................................................................................
Branch Instructions122................................................................................................................................................................
Branch With Link122................................................................................................................................................................
Coprocessor Instructions123................................................................................................................................................................
The Arm9 Instruction Set123................................................................................................................................................................
Table 4-1 Arm920t Instruction Set123................................................................................................................................................................
The Arm Thumb Instruction Set124................................................................................................................................................................
Table 4-2 Arm Thumb Instruction Set124................................................................................................................................................................
Arm920t Modes And Registers125................................................................................................................................................................
Table 4-3 Register Availability By Mode125................................................................................................................................................................
Introduction To The Etm127................................................................................................................................................................
Figure 5-1 Etm Block Diagram127................................................................................................................................................................
Programming And Reading Etm Registers128................................................................................................................................................................
Pin Configuration For Etm128................................................................................................................................................................
Table 5-1 Etm Pin Configuration128................................................................................................................................................................
Functional Description Of The Reset Module129................................................................................................................................................................
Global Reset129................................................................................................................................................................
Figure 6-1 Reset Module Block Diagram129................................................................................................................................................................
Arm920t Processor Reset130................................................................................................................................................................
Figure 6-2 Dram And Internal Reset Timing Diagram130................................................................................................................................................................
Programming Model131................................................................................................................................................................
Reset Source Register (rsr)131................................................................................................................................................................
Table 6-1 Reset Module Pin And Signal Descriptions131................................................................................................................................................................
Table 6-2 Rsr Register Description132................................................................................................................................................................
Table 6-3 Hardware Reset Source Matrix132................................................................................................................................................................
Overview133................................................................................................................................................................
General Information133................................................................................................................................................................
Figure 7-1 Aipi Interface134................................................................................................................................................................
Figure 7-2 Block Diagram Of The Aipi Module135................................................................................................................................................................
Table 7-1 R-ahb To Ip Bus Interface Operation (big Endian—read Operation)136................................................................................................................................................................
Table 7-2 R-ahb To Ip Bus Interface Operation (big Endian—write Operation)137................................................................................................................................................................
Table 7-3 R-ahb To Ip Bus Interface Operation (little Endian—read Operation)139................................................................................................................................................................
Table 7-4 R-ahb To Ip Bus Interface Operation (little Endian—write Operation)140................................................................................................................................................................
Table 7-5 Aipi Module Register Memory Map142................................................................................................................................................................
Table 7-6 Peripheral Address Module_en Numbers142................................................................................................................................................................
Peripheral Size Registers[1:0]144................................................................................................................................................................
Aipi1 Peripheral Size Register 0 And Aipi2 Peripheral Size Register 0144................................................................................................................................................................
And Aipi2 Peripheral Size Register 0 Description144................................................................................................................................................................
Aipi1 Peripheral Size Register 1 And Aipi2 Peripheral Size Register 1145................................................................................................................................................................
And Aipi2 Peripheral Size Register 1 Description145................................................................................................................................................................
Peripheral Access Registers146................................................................................................................................................................
Table 7-9 Psr Data Bus Size Encoding146................................................................................................................................................................
Peripheral Control Register147................................................................................................................................................................
Table 7-10 Peripheral Access Register Description147................................................................................................................................................................
Time-out Status Register148................................................................................................................................................................
Table 7-11 Peripheral Control Register Description148................................................................................................................................................................
Programming Example149................................................................................................................................................................
Data Access To 8-bit Peripherals149................................................................................................................................................................
Table 7-12 Time-out Status Register Description149................................................................................................................................................................
Data Access To 16-bit Peripherals150................................................................................................................................................................
Table 7-13 Core And 8-bit Peripheral Register Content After Code Execution150................................................................................................................................................................
Table 7-14 Core And 16-bit Peripheral Register Content (little Endian)150................................................................................................................................................................
Data Access To 32-bit Peripherals151................................................................................................................................................................
Table 7-15 Core And 16-bit Peripheral Register Content (big Endian)151................................................................................................................................................................
Special Consideration For Non-natural Size Access152................................................................................................................................................................
Table 7-16 Core And 32-bit Peripheral Register Content (little Endian)152................................................................................................................................................................
Table 7-17 Core And 32-bit Peripheral Register Content (big Endian)152................................................................................................................................................................
Table 8-1 System Control Module Register Memory Map153................................................................................................................................................................
Silicon Id Register154................................................................................................................................................................
Table 8-2 Silicon Id Register Description154................................................................................................................................................................
Function Multiplexing Control Register155................................................................................................................................................................
Table 8-3 Function Multiplexing Control Register Description155................................................................................................................................................................
Global Peripheral Control Register156................................................................................................................................................................
Table 8-4 Global Peripheral Control Register Description157................................................................................................................................................................
Global Clock Control Register158................................................................................................................................................................
Table 8-5 Global Clock Control Register Description158................................................................................................................................................................
System Boot Mode Selection159................................................................................................................................................................
Table 8-6 System Boot Mode Selection159................................................................................................................................................................
Operation161................................................................................................................................................................
Entering Bootstrap Mode162................................................................................................................................................................
Bootstrap Record Format162................................................................................................................................................................
Table 9-1 Bootstrap Record Format162................................................................................................................................................................
Table 9-2 Definition Of Count/mode Byte162................................................................................................................................................................
Registers Used In Bootloader Program163................................................................................................................................................................
Setting Up The Rs-232 Terminal163................................................................................................................................................................
Changing The Speed Of Communication163................................................................................................................................................................
B-record Example163................................................................................................................................................................
Instruction Buffer Usage163................................................................................................................................................................
Table 9-3 Program Breakdown164................................................................................................................................................................
Table 9-4 Resulting B-records164................................................................................................................................................................
Simple Read/write Examples165................................................................................................................................................................
Table 9-5 Read/write Examples165................................................................................................................................................................
Bootloader Flowchart167................................................................................................................................................................
Special Notes167................................................................................................................................................................
Figure 9-1 Bootloader Program Operation167................................................................................................................................................................
Figure 10-1 Aitc Block Diagram169................................................................................................................................................................
Aitc Interrupt Controller Signals171................................................................................................................................................................
Table 10-1 Interrupt Assignment171................................................................................................................................................................
Table 10-2 Aitc Module Register Memory Map172................................................................................................................................................................
Table 10-3 Register Field Summary174................................................................................................................................................................
Interrupt Control Register175................................................................................................................................................................
Table 10-4 Interrupt Control Register Description175................................................................................................................................................................
Normal Interrupt Mask Register177................................................................................................................................................................
Table 10-5 Normal Interrupt Mask Register Description177................................................................................................................................................................
Interrupt Enable Number Register178................................................................................................................................................................
Table 10-6 Interrupt Enable Number Register Description178................................................................................................................................................................
Interrupt Disable Number Register179................................................................................................................................................................
Table 10-7 Interrupt Disable Number Register Description179................................................................................................................................................................
Interrupt Enable Register High And Interrupt Enable Register Low180................................................................................................................................................................
Interrupt Enable Register High180................................................................................................................................................................
Table 10-8 Interrupt Enable Register High Description180................................................................................................................................................................
Interrupt Enable Register Low181................................................................................................................................................................
Table 10-9 Interrupt Enable Register Low Description181................................................................................................................................................................
Interrupt Type Register High And Interrupt Type Register Low182................................................................................................................................................................
Interrupt Type Register High182................................................................................................................................................................
Table 10-10 Interrupt Type Register High Description182................................................................................................................................................................
Interrupt Type Register Low183................................................................................................................................................................
Normal Interrupt Priority Level Registers183................................................................................................................................................................
Table 10-11 Interrupt Type Register Low Description183................................................................................................................................................................
Normal Interrupt Priority Level Register 7184................................................................................................................................................................
Table 10-12 Normal Interrupt Priority Level Register 7 Description184................................................................................................................................................................
Normal Interrupt Priority Level Register 6185................................................................................................................................................................
Table 10-13 Normal Interrupt Priority Level Register 6 Description185................................................................................................................................................................
Normal Interrupt Priority Level Register 5186................................................................................................................................................................
Table 10-14 Normal Interrupt Priority Level Register 5 Description186................................................................................................................................................................
Normal Interrupt Priority Level Register 4187................................................................................................................................................................
Table 10-15 Normal Interrupt Priority Level Register 4 Description187................................................................................................................................................................
Normal Interrupt Priority Level Register 3188................................................................................................................................................................
Table 10-16 Normal Interrupt Priority Level Register 3 Description188................................................................................................................................................................
Normal Interrupt Priority Level Register 2189................................................................................................................................................................
Table 10-17 Normal Interrupt Priority Level Register 2 Description189................................................................................................................................................................
Normal Interrupt Priority Level Register 1190................................................................................................................................................................
Table 10-18 Normal Interrupt Priority Level Register 1 Description190................................................................................................................................................................
Normal Interrupt Priority Level Register 0191................................................................................................................................................................
Table 10-19 Normal Interrupt Priority Level Register 0 Description191................................................................................................................................................................
Normal Interrupt Vector And Status Register192................................................................................................................................................................
Table 10-20 Normal Interrupt Vector And Status Register Description192................................................................................................................................................................
Fast Interrupt Vector And Status Register193................................................................................................................................................................
Table 10-21 Fast Interrupt Vector And Status Register Description193................................................................................................................................................................
Interrupt Source Register High And Interrupt Source Register Low194................................................................................................................................................................
Interrupt Source Register High194................................................................................................................................................................
Table 10-22 Interrupt Source Register High Description194................................................................................................................................................................
Interrupt Source Register Low195................................................................................................................................................................
Table 10-23 Interrupt Source Register Low Description195................................................................................................................................................................
Interrupt Force Register High And Interrupt Force Register Low196................................................................................................................................................................
Interrupt Force Register High196................................................................................................................................................................
Table 10-24 Interrupt Force Register High Description196................................................................................................................................................................
Interrupt Force Register Low197................................................................................................................................................................
Table 10-25 Interrupt Force Register Low Description197................................................................................................................................................................
And Normal Interrupt Pending Register Low198................................................................................................................................................................
Normal Interrupt Pending Register High198................................................................................................................................................................
Table 10-26 Normal Interrupt Pending Register High Description198................................................................................................................................................................
Normal Interrupt Pending Register Low199................................................................................................................................................................
Table 10-27 Normal Interrupt Pending Register Low Description199................................................................................................................................................................
Fast Interrupt Pending Register High And Fast Interrupt Pending Register Low200................................................................................................................................................................
Fast Interrupt Pending Register High200................................................................................................................................................................
Table 10-28 Fast Interrupt Pending Register High Description200................................................................................................................................................................
Fast Interrupt Pending Register Low201................................................................................................................................................................
Table 10-29 Fast Interrupt Pending Register Low Description201................................................................................................................................................................
Arm920t Processor Interrupt Controller Operation202................................................................................................................................................................
Arm920t Processor Prioritization Of Exception Sources202................................................................................................................................................................
Aitc Prioritization Of Interrupt Sources202................................................................................................................................................................
Assigning And Enabling Interrupt Sources202................................................................................................................................................................
Enabling Interrupts Sources202................................................................................................................................................................
Typical Interrupt Entry Sequences203................................................................................................................................................................
Table 10-30 Typical Hardware Accelerated Normal Interrupt Entry Sequence203................................................................................................................................................................
Table 10-31 Typical Fast Interrupt Entry Sequence203................................................................................................................................................................
Writing Reentrant Normal Interrupt Routines204................................................................................................................................................................
Eim I/o Signals205................................................................................................................................................................
Address Bus205................................................................................................................................................................
Data Bus205................................................................................................................................................................
Read/write206................................................................................................................................................................
Control Signals206................................................................................................................................................................
Oe—output Enable206................................................................................................................................................................
Eb [3:0]—enable Bytes206................................................................................................................................................................
Dtack—data Transfer Acknowledge206................................................................................................................................................................
Chip Select Outputs206................................................................................................................................................................
Chip Select 0 (cs0)206................................................................................................................................................................
Chip Select 1–chip Select 5 (cs1–cs5)206................................................................................................................................................................
Burst Mode Signals207................................................................................................................................................................
Bclk—burst Clock207................................................................................................................................................................
Lba—load Burst Address207................................................................................................................................................................
Ecb—end Current Burst207................................................................................................................................................................
Pin Configuration For Eim207................................................................................................................................................................
Table 11-1 Chip Select Address Range207................................................................................................................................................................
Table 11-2 Eim Pin List208................................................................................................................................................................
Table 11-3 Pin Configuration208................................................................................................................................................................
Typical Eim System Connections210................................................................................................................................................................
Figure 11-1 Example Of Eim Interface To Memory And Peripherals210................................................................................................................................................................
Figure 11-2 Example Of Eim Interface To Burst Memory211................................................................................................................................................................
Eim Functionality212................................................................................................................................................................
Configurable Bus Sizing212................................................................................................................................................................
Programmable Output Generation212................................................................................................................................................................
Burst Mode Operation212................................................................................................................................................................
Burst Clock Divisor212................................................................................................................................................................
Burst Clock Start213................................................................................................................................................................
Page Mode Emulation213................................................................................................................................................................
Error Conditions213................................................................................................................................................................
Table 11-4 Eim Module Register Memory Map214................................................................................................................................................................
Chip Select 0 Control Registers215................................................................................................................................................................
Chip Select 0 Upper Control Register215................................................................................................................................................................
Chip Select 0 Lower Control Register215................................................................................................................................................................
Chip Select 1–chip Select 5 Control Registers216................................................................................................................................................................
Table 11-5 Chip Select Control Registers Description217................................................................................................................................................................
Table 11-6 Chip Select Wait State And Burst Delay Encoding222................................................................................................................................................................
Eim Configuration Register225................................................................................................................................................................
Table 11-7 Eim Configuration Register Description225................................................................................................................................................................
Clock Sources227................................................................................................................................................................
Low Frequency Clock Source227................................................................................................................................................................
High Frequency Clock Source228................................................................................................................................................................
Figure 12-1 Clock Controller Module228................................................................................................................................................................
Table 12-1 Clock Controller Module Signal Descriptions228................................................................................................................................................................
Dpll Output Frequency Calculation229................................................................................................................................................................
Dpll Phase And Frequency Jitter229................................................................................................................................................................
Mc9328mx1 Power Management230................................................................................................................................................................
Pll Operation At Power-up230................................................................................................................................................................
Pll Operation At Wake-up230................................................................................................................................................................
Arm920t Processor Low-power Modes230................................................................................................................................................................
Sdram Power Modes230................................................................................................................................................................
Power Management In The Clock Controller230................................................................................................................................................................
Table 12-2 Sdram/syncflash Operation During Power Modes230................................................................................................................................................................
Clock Source Control Register231................................................................................................................................................................
Table 12-3 Power Management In The Clock Controller231................................................................................................................................................................
Table 12-4 Pll And Clock Controller Module Register Memory Map231................................................................................................................................................................
Table 12-5 Clock Source Control Register Description232................................................................................................................................................................
Peripheral Clock Divider Register234................................................................................................................................................................
Table 12-6 Clock Sources For Peripherals234................................................................................................................................................................
Table 12-7 Peripheral Clock Divider Register Description234................................................................................................................................................................
Programming Digital Phase Locked Loops235................................................................................................................................................................
Mcu Pll Control Register 0235................................................................................................................................................................
Table 12-8 Sample Frequency Table235................................................................................................................................................................
Table 12-9 Mcu Pll Control Register 0 Description236................................................................................................................................................................
Mcu Pll And System Clock Control Register 1237................................................................................................................................................................
Generation Of 48 Mhz Clocks237................................................................................................................................................................
Table 12-10 Mcu Pll And System Clock Control Register 1 Description237................................................................................................................................................................
Table 12-11 System Pll Multiplier Factor237................................................................................................................................................................
Mcu Pll And System Clock Control Register237................................................................................................................................................................
System Pll Control Register 0238................................................................................................................................................................
Table 12-12 System Pll Control Register 0 Description238................................................................................................................................................................
System Pll Control Register 1239................................................................................................................................................................
Table 12-13 System Pll Control Register 1 Description239................................................................................................................................................................
Figure 13-1 Dmac In Mc9328mx1242................................................................................................................................................................
Figure 13-2 Dmac Block Diagram242................................................................................................................................................................
Signal Description243................................................................................................................................................................
Figure 13-3 Dma Request And Acknowledge Timing Diagram243................................................................................................................................................................
Figure 13-4 2d Memory Diagram243................................................................................................................................................................
Table 13-1 Signal Description243................................................................................................................................................................
Big Endian And Little Endian244................................................................................................................................................................
Table 13-2 Dma Module Register Memory Map244................................................................................................................................................................
General Registers248................................................................................................................................................................
Dma Control Register248................................................................................................................................................................
Table 13-3 Dma Control Register Description248................................................................................................................................................................
Dma Interrupt Status Register249................................................................................................................................................................
Table 13-4 Dma Interrupt Status Register Description249................................................................................................................................................................
Dma Interrupt Mask Register250................................................................................................................................................................
Table 13-5 Dma Interrupt Mask Register Description250................................................................................................................................................................
Dma Burst Time-out Status Register251................................................................................................................................................................
Table 13-6 Dma Burst Time-out Status Register Description251................................................................................................................................................................
Dma Request Time-out Status Register252................................................................................................................................................................
Table 13-7 Dma Request Time-out Status Register Description252................................................................................................................................................................
Dma Transfer Error Status Register253................................................................................................................................................................
Table 13-8 Dma Transfer Error Status Register Description253................................................................................................................................................................
Dma Buffer Overflow Status Register254................................................................................................................................................................
Table 13-9 Dma Buffer Overflow Status Register Description254................................................................................................................................................................
Dma Burst Time-out Control Register255................................................................................................................................................................
Table 13-10 Dma Burst Time-out Control Register Description255................................................................................................................................................................
D Memory Registers (a And B)256................................................................................................................................................................
W-size Registers256................................................................................................................................................................
Table 13-11 W-size Registers Description256................................................................................................................................................................
X-size Registers257................................................................................................................................................................
Table 13-12 X-size Registers Description257................................................................................................................................................................
Y-size Registers258................................................................................................................................................................
Channel Registers258................................................................................................................................................................
Table 13-13 Y-size Registers Description258................................................................................................................................................................
Channel Source Address Register259................................................................................................................................................................
Table 13-14 Channel Source Address Register Description259................................................................................................................................................................
Destination Address Registers260................................................................................................................................................................
Table 13-15 Channel Destination Address Registers Description260................................................................................................................................................................
Channel Count Registers261................................................................................................................................................................
Table 13-16 Channel Count Registers Description261................................................................................................................................................................
Channel Control Registers262................................................................................................................................................................
Table 13-17 Channel Control Registers Description263................................................................................................................................................................
Table 13-18 Dma_eobo_cnt And Dma_eobi_cnt Settings264................................................................................................................................................................
Channel Request Source Select Registers265................................................................................................................................................................
Table 13-19 Channel Request Source Select Registers Description265................................................................................................................................................................
Channel Burst Length Registers266................................................................................................................................................................
Table 13-20 Channel Burst Length Registers Description266................................................................................................................................................................
Channel Request Time-out Registers267................................................................................................................................................................
Channel 0 Bus Utilization Control Register268................................................................................................................................................................
Table 13-21 Channel Request Time-out Registers Description268................................................................................................................................................................
Table 13-22 Channel 0 Bus Utilization Control Registers Description269................................................................................................................................................................
Dma Request Table270................................................................................................................................................................
Table 13-23 Dma Request Table270................................................................................................................................................................
General Overview273................................................................................................................................................................
Watchdog Timer Operation273................................................................................................................................................................
Timing Specifications273................................................................................................................................................................
Figure 14-1 Watchdog Timer Functional Block Diagram273................................................................................................................................................................
Watchdog During Reset274................................................................................................................................................................
Power-on Reset274................................................................................................................................................................
Software Reset274................................................................................................................................................................
Watchdog After Reset274................................................................................................................................................................
Initial Load274................................................................................................................................................................
Countdown274................................................................................................................................................................
Reload274................................................................................................................................................................
Time-out275................................................................................................................................................................
Halting The Counter275................................................................................................................................................................
Watchdog Control275................................................................................................................................................................
Interrupt Control275................................................................................................................................................................
Reset Sources275................................................................................................................................................................
State Machine276................................................................................................................................................................
Figure 14-2 Counter State Machine276................................................................................................................................................................
Watchdog Timer I/o Signals277................................................................................................................................................................
Table 14-1 Watchdog Timer I/o Signals277................................................................................................................................................................
Watchdog Control Register278................................................................................................................................................................
Table 14-2 Watchdog Control Register Description278................................................................................................................................................................
Watchdog Service Register279................................................................................................................................................................
Watchdog Status Register280................................................................................................................................................................
Table 14-3 Watchdog Service Register Description280................................................................................................................................................................
Table 14-4 Watchdog Status Register Description280................................................................................................................................................................
Asp Signal Description283................................................................................................................................................................
Figure 15-1 Asp System Block Diagram283................................................................................................................................................................
Figure 15-2 Simplified Asp Signal Path Diagram284................................................................................................................................................................
Table 15-1 Asp Interface Signal Description284................................................................................................................................................................
Interrupt Generation285................................................................................................................................................................
Pen Adc (padc) Operation285................................................................................................................................................................
Table 15-2 Simplified Asp Signal Path Parameters285................................................................................................................................................................
Current-mode Operation286................................................................................................................................................................
Table 15-3 Pen Adc Operation286................................................................................................................................................................
Sample Rate Control287................................................................................................................................................................
Figure 15-3 Pen Input Sampling Timing287................................................................................................................................................................
Table 15-4 Pen Adc Maximum Sample Rate287................................................................................................................................................................
Table 15-5 Output Data Rate Equations288................................................................................................................................................................
Auto-zero Function289................................................................................................................................................................
Pen-down Detection289................................................................................................................................................................
Pen-up Detection (method 1 – Compare Value)289................................................................................................................................................................
Pen-up Detection (method 2 – Detect Rising Edge)289................................................................................................................................................................
Temperature Compensation289................................................................................................................................................................
Table 15-6 Asp Module Register Memory Map290................................................................................................................................................................
Asp Control Register291................................................................................................................................................................
Table 15-7 Control Register Description291................................................................................................................................................................
Pen A/d Sample Rate Control Register293................................................................................................................................................................
Table 15-8 Pen A/d Sample Rate Control Register Description293................................................................................................................................................................
Compare Control Register294................................................................................................................................................................
Table 15-9 Compare Control Register Description294................................................................................................................................................................
Table 15-10 Interrupt Control Register Description295................................................................................................................................................................
Interrupt/error Status Register296................................................................................................................................................................
Table 15-11 Interrupt/error Status Register Description296................................................................................................................................................................
Pen Sample Fifo297................................................................................................................................................................
Clock Divide Register298................................................................................................................................................................
Table 15-12 Pen Sample Fifo Register Description298................................................................................................................................................................
Table 15-13 Clock Divide Register Description298................................................................................................................................................................
Asp Fifo Pointer Register299................................................................................................................................................................
Table 15-14 Asp Fifo Pointer Register Description299................................................................................................................................................................
Bluetooth Primer301................................................................................................................................................................
Bta Overview302................................................................................................................................................................
Figure 16-1 Functional Blocks In A Bluetooth System302................................................................................................................................................................
Module Descriptions303................................................................................................................................................................
Bluetooth Core303................................................................................................................................................................
Figure 16-2 Functional Blocks In The Bluetooth Accelerator303................................................................................................................................................................
Ip Bus Interface304................................................................................................................................................................
Table 16-1 Clk_control Register Settings For Synchronization304................................................................................................................................................................
Sequencer305................................................................................................................................................................
Bluetooth Clocks305................................................................................................................................................................
Table 16-2 Bluetooth Clocks And Counters305................................................................................................................................................................
Bluetooth Pipeline Processor307................................................................................................................................................................
Table 16-3 Bluetooth Core Interrupts307................................................................................................................................................................
Hec/crc Generator And Checker308................................................................................................................................................................
Figure 16-3 Bluetooth Packet Format308................................................................................................................................................................
Table 16-4 Packet Types And Fec/crc Processing309................................................................................................................................................................
Encryption And Decryption Engine310................................................................................................................................................................
Table 16-5 Writing Sequence For Encryption Engine Initialization310................................................................................................................................................................
Whitening/de-whitening311................................................................................................................................................................
Fec Coding/decoding311................................................................................................................................................................
Bit Buffer311................................................................................................................................................................
Correlator312................................................................................................................................................................
Figure 16-4 Bitbuf Memory312................................................................................................................................................................
Table 16-6 Functions Using The Bit Buffer312................................................................................................................................................................
Bluetooth Application Timer313................................................................................................................................................................
Hop Selection Co-processor313................................................................................................................................................................
Radio Control313................................................................................................................................................................
Table 16-7 Hop Selection Co-processor Writing Sequence313................................................................................................................................................................
Frequency Synthesizer And Timing Control314................................................................................................................................................................
Pulse Width Modulators314................................................................................................................................................................
Radio Module Interfaces314................................................................................................................................................................
Table 16-8 Bluetooth Pin Mapping For Various Radio Interfaces314................................................................................................................................................................
Figure 16-5 Programming Interfaces For The Mc13180 Radio315................................................................................................................................................................
Figure 16-6 Timing Of The Rf Module Control Signals For The Mc13180 Radio316................................................................................................................................................................
Figure 16-7 Programming Interface For The Siwave Radio317................................................................................................................................................................
Figure 16-8 Timing Of Rf Module Control Signals For The Siwave Radio317................................................................................................................................................................
Wake-up Module318................................................................................................................................................................
Figure 16-9 Block Diagram Of The Wake-up Module318................................................................................................................................................................
Pin Configuration For Bta319................................................................................................................................................................
Figure 16-10 Timing Of The Wake-up Signals319................................................................................................................................................................
Table 16-9 Pin Configuration320................................................................................................................................................................
Table 16-10 Bta Module Register Memory Map321................................................................................................................................................................
Table 16-11 Bta Module Register Overview323................................................................................................................................................................
Sequencer Registers326................................................................................................................................................................
Command Register326................................................................................................................................................................
Table 16-12 Command Register Description326................................................................................................................................................................
Status Register327................................................................................................................................................................
Table 16-13 Status Register Description328................................................................................................................................................................
Packet Header Register329................................................................................................................................................................
Table 16-14 Packet Header Register Description329................................................................................................................................................................
Payload Header Register330................................................................................................................................................................
Table 16-15 Payload Header Register Description330................................................................................................................................................................
Bluetooth Clocks Registers331................................................................................................................................................................
Native Count Register331................................................................................................................................................................
Table 16-16 Native Count Register Description331................................................................................................................................................................
Estimated Count Register332................................................................................................................................................................
Table 16-17 Estimated Count Register Description332................................................................................................................................................................
Offset Count Register333................................................................................................................................................................
Table 16-18 Offset Count Register Description333................................................................................................................................................................
Native Clock Low Register334................................................................................................................................................................
Table 16-19 Native Clock Low Register Description334................................................................................................................................................................
Native Clock High Register335................................................................................................................................................................
Table 16-20 Native Clock High Register Description335................................................................................................................................................................
Estimated Clock Low Register336................................................................................................................................................................
Table 16-21 Estimated Clock Low Register Description336................................................................................................................................................................
Estimated Clock High Register337................................................................................................................................................................
Table 16-22 Estimated Clock High Register Description337................................................................................................................................................................
Offset Clock Low Register338................................................................................................................................................................
Table 16-23 Offset Clock Low Register Description338................................................................................................................................................................
Offset Clock High Register339................................................................................................................................................................
Table 16-24 Offset Clock High Register Description339................................................................................................................................................................
Bluetooth Pipeline Registers340................................................................................................................................................................
Heccrc Control Register340................................................................................................................................................................
Table 16-25 Heccrc Control Register Description340................................................................................................................................................................
White Control Register341................................................................................................................................................................
Table 16-26 White Control Register Description341................................................................................................................................................................
Encryption Control X13 Register342................................................................................................................................................................
Table 16-27 Encryption Control X13 Register Description342................................................................................................................................................................
Radio Control Registers343................................................................................................................................................................
Correlation Time Setup Register343................................................................................................................................................................
Table 16-28 Correlation Time Setup Register Description343................................................................................................................................................................
Correlation Time Stamp Register344................................................................................................................................................................
Table 16-29 Correlation Time Stamp Register Description344................................................................................................................................................................
Rf Gpo Register345................................................................................................................................................................
Table 16-30 Rf Gpo Register Description345................................................................................................................................................................
Pwm Received Signal Strength Indicator Register346................................................................................................................................................................
Table 16-31 Pwm Received Signal Strength Indicator Register Description (mc13180)346................................................................................................................................................................
Time A & B Register347................................................................................................................................................................
Table 16-32 Time A & B Register Description347................................................................................................................................................................
Time C & D Register348................................................................................................................................................................
Table 16-33 Time C & D Register Description348................................................................................................................................................................
Pwm Tx Register349................................................................................................................................................................
Table 16-34 Pwm Tx Register Description349................................................................................................................................................................
Rf Control Register350................................................................................................................................................................
Table 16-35 Rf Control Register Description350................................................................................................................................................................
Rf Status Register352................................................................................................................................................................
Table 16-36 Rf Status Register Description352................................................................................................................................................................
Rx Time Register354................................................................................................................................................................
Table 16-37 Rx Time Register Description354................................................................................................................................................................
Tx Time Register355................................................................................................................................................................
Table 16-38 Tx Time Register Description355................................................................................................................................................................
Timer Register356................................................................................................................................................................
Bluetooth Application Timer Register356................................................................................................................................................................
Table 16-39 Bluetooth Application Timer Register Description356................................................................................................................................................................
Correlator Registers357................................................................................................................................................................
Threshold Register357................................................................................................................................................................
Table 16-40 Threshold Register Description (mc13180)357................................................................................................................................................................
Table 16-41 Threshold Register Description (siliconwave)358................................................................................................................................................................
Table 16-42 Signal Energy Levels And Threshold Levels358................................................................................................................................................................
Correlation Max Register359................................................................................................................................................................
Table 16-43 Correlation Max Register Description359................................................................................................................................................................
Synch Word 0 Register360................................................................................................................................................................
Table 16-44 Synch Word 0 Register Description360................................................................................................................................................................
Synch Word 1 Register361................................................................................................................................................................
Table 16-45 Synch Word 1 Register Description361................................................................................................................................................................
Synch Word 2 Register362................................................................................................................................................................
Synch Word 3 Register362................................................................................................................................................................
Table 16-46 Synch Word 2 Register Description362................................................................................................................................................................
Bit Buffer Registers363................................................................................................................................................................
Buffer Word Registers363................................................................................................................................................................
Table 16-47 Synch Word 3 Register Description363................................................................................................................................................................
Table 16-48 Buf Word 0 (lw0) Register To Buf Word 31 (lw7) Register Description363................................................................................................................................................................
Table 16-49 Bit Buffer Registers Numbers And Addresses364................................................................................................................................................................
Wake-up Registers365................................................................................................................................................................
Wake-up 1 Register365................................................................................................................................................................
Table 16-50 Wake-up 1 Register Description365................................................................................................................................................................
Wake-up 2 Register366................................................................................................................................................................
Table 16-51 Wake-up 2 Register Description366................................................................................................................................................................
Wake-up Delta4 Register367................................................................................................................................................................
Table 16-52 Wake-up Delta4 Register Description367................................................................................................................................................................
Wake-up 4 Register368................................................................................................................................................................
Table 16-53 Wake-up 4 Register Description368................................................................................................................................................................
Wakeup Control Register369................................................................................................................................................................
Table 16-54 Wakeup Control Register Description369................................................................................................................................................................
Wake-up Status Register370................................................................................................................................................................
Table 16-55 Wake-up Status Register Description370................................................................................................................................................................
Wake-up Count Register371................................................................................................................................................................
Table 16-56 Wake-up Count Register Description371................................................................................................................................................................
System Register372................................................................................................................................................................
Clock Control Register372................................................................................................................................................................
Table 16-57 Clock Control Register Description372................................................................................................................................................................
Spi Registers373................................................................................................................................................................
Spi Word0 Register373................................................................................................................................................................
Table 16-58 Spi Word0 Register Description (mc13180)373................................................................................................................................................................
Spi Word1 Register374................................................................................................................................................................
Table 16-59 Spi Word0 Register Description (siliconwave)374................................................................................................................................................................
Table 16-60 Spi Word1 Register Description (mc13180)374................................................................................................................................................................
Spi Word2 Register375................................................................................................................................................................
Table 16-61 Spi Word1 Register Description (siliconwave)375................................................................................................................................................................
Table 16-62 Spi Word2 Register Description (mc13180)375................................................................................................................................................................
Table 16-63 Spi Word2 Register Description (siliconwave)375................................................................................................................................................................
Spi Word3 Register376................................................................................................................................................................
Table 16-64 Spi Word3 Register Description (mc13180)376................................................................................................................................................................
Table 16-65 Spi Word3 Register Description (siliconwave)376................................................................................................................................................................
Spi Write Address Register377................................................................................................................................................................
Table 16-66 Spi Write Address Register Description (mc13180)377................................................................................................................................................................
Spi Read Address Register378................................................................................................................................................................
Table 16-67 Spi Write Address Register Description (siliconwave)378................................................................................................................................................................
Table 16-68 Spi Read Address Register Description (mc13180)378................................................................................................................................................................
Spi Control Register379................................................................................................................................................................
Table 16-69 Spi Read Address Register Description (siliconwave)379................................................................................................................................................................
Figure 16-11 Spi Clock Dividers Determine Duty Cycle Of Spi Clock380................................................................................................................................................................
Table 16-70 Spi Control Register Description380................................................................................................................................................................
Spi Status Register381................................................................................................................................................................
Frequency Hopping Registers381................................................................................................................................................................
Table 16-71 Spi Status Register Description381................................................................................................................................................................
Hop 0 (frequency In) Register382................................................................................................................................................................
Hop 1 (frequency In) Register382................................................................................................................................................................
Table 16-72 Hop 0 (frequency In) Register Description382................................................................................................................................................................
Hop 2 (frequency In) Register383................................................................................................................................................................
Table 16-73 Hop 1 (frequency In) Register Description383................................................................................................................................................................
Table 16-74 Hop 2 (frequency In) Register Description383................................................................................................................................................................
Hop 3 (frequency In) Register384................................................................................................................................................................
Hop 4 (frequency In) Register384................................................................................................................................................................
Table 16-75 Hop 3 (frequency In) Register Description384................................................................................................................................................................
Hop Frequency Out Register385................................................................................................................................................................
Table 16-76 Hop 4 (frequency In) Register Description385................................................................................................................................................................
Table 16-77 Hop Frequency Out Register Description385................................................................................................................................................................
Interrupt Register386................................................................................................................................................................
Interrupt Vector Register386................................................................................................................................................................
Table 16-78 Interrupt Vector Register Description386................................................................................................................................................................
Joint Detect Registers387................................................................................................................................................................
Synchronization Metric Register387................................................................................................................................................................
Table 16-79 Synchronization Metric Register Description387................................................................................................................................................................
Synchronize Frequency Carrier Register388................................................................................................................................................................
Bit Reverse Registers388................................................................................................................................................................
Word Reverse Register388................................................................................................................................................................
Table 16-80 Synchronize Frequency Carrier Register Description388................................................................................................................................................................
Byte Reverse Register389................................................................................................................................................................
Table 16-81 Word Reverse Register Description389................................................................................................................................................................
Table 16-82 Byte Reverse Register Description390................................................................................................................................................................
Mma Operation391................................................................................................................................................................
Memory Access391................................................................................................................................................................
Basic Mac Operation392................................................................................................................................................................
Data Access392................................................................................................................................................................
Figure 17-1 Mma Data Access392................................................................................................................................................................
Cache393................................................................................................................................................................
Figure 17-2 Circular Buffering Operation393................................................................................................................................................................
Dct/idct394................................................................................................................................................................
Figure 17-3 Dct/idct Architecture394................................................................................................................................................................
Figure 17-4 Data Formatting For Dct And Idct394................................................................................................................................................................
Table 17-1 Mma Module Register Memory Map395................................................................................................................................................................
Mma Mac Control Registers396................................................................................................................................................................
Mma Mac Module Register396................................................................................................................................................................
Table 17-2 Mma Mac Module Register Description396................................................................................................................................................................
Mma Mac Control Register397................................................................................................................................................................
Table 17-3 Mma Mac Control Register Description397................................................................................................................................................................
Mma Mac Multiply Counter Register399................................................................................................................................................................
Table 17-4 Mma Mac Multiply Counter Register Description399................................................................................................................................................................
Mma Mac Accumulate Counter Register400................................................................................................................................................................
Mma Mac Interrupt Register400................................................................................................................................................................
Table 17-5 Mma Mac Accumulate Counter Register Description400................................................................................................................................................................
Mma Mac Interrupt Mask Register401................................................................................................................................................................
Table 17-6 Mma Mac Interrupt Register Description401................................................................................................................................................................
Table 17-7 Mma Mac Interrupt Mask Register Description401................................................................................................................................................................
Mma Mac Fifo Register402................................................................................................................................................................
Table 17-8 Mma Mac Fifo Register Description402................................................................................................................................................................
Mma Mac Fifo Status Register403................................................................................................................................................................
Table 17-9 Mma Mac Fifo Status Register Description403................................................................................................................................................................
Mma Mac Burst Count Register404................................................................................................................................................................
Mma Mac Bit Select Register404................................................................................................................................................................
Table 17-10 Mma Mac Burst Count Register Description404................................................................................................................................................................
Mma Mac Xy Count Accumulate Register405................................................................................................................................................................
Mma Mac X Register Control Registers405................................................................................................................................................................
Table 17-11 Mma Mac Bit Select Register Description405................................................................................................................................................................
Mma Mac X Base Address Register406................................................................................................................................................................
Mma Mac X Index Register406................................................................................................................................................................
Table 17-12 Mma Mac X Base Address Register Description406................................................................................................................................................................
Table 17-13 Mma Mac X Index Register Description406................................................................................................................................................................
Mma Mac X Length Register407................................................................................................................................................................
Table 17-14 Mma Mac X Length Register Description407................................................................................................................................................................
Mma Mac X Modify Register408................................................................................................................................................................
Mma Mac X Increment Register408................................................................................................................................................................
Table 17-15 Mma Mac X Modify Register Description408................................................................................................................................................................
Mma Mac X Count Register409................................................................................................................................................................
Mma Mac Y Register Control Registers409................................................................................................................................................................
Table 17-16 Mma Mac X Increment Register Description409................................................................................................................................................................
Table 17-17 Mma Mac X Count Register Description409................................................................................................................................................................
Mma Mac Y Base Address Register410................................................................................................................................................................
Mma Mac Y Index Register410................................................................................................................................................................
Table 17-18 Mma Mac Y Base Address Register Description410................................................................................................................................................................
Table 17-19 Mma Mac Y Index Register Description410................................................................................................................................................................
Mma Mac Y Length Register411................................................................................................................................................................
Table 17-20 Mma Mac Y Length Register Description411................................................................................................................................................................
Mma Mac Y Modify Register412................................................................................................................................................................
Mma Mac Y Increment Register412................................................................................................................................................................
Table 17-21 Mma Mac Y Modify Register Description412................................................................................................................................................................
Mma Mac Y Count Register413................................................................................................................................................................
Table 17-22 Mma Mac Y Increment Register Description413................................................................................................................................................................
Table 17-23 Mma Mac Y Count Register Description413................................................................................................................................................................
Mma Dct/idct Registers414................................................................................................................................................................
Dct/idct Control Register414................................................................................................................................................................
Table 17-24 Dct/idct Control Register Description414................................................................................................................................................................
Dct/idct Version Register415................................................................................................................................................................
Table 17-25 Dct/idct Version Register Description415................................................................................................................................................................
Dct/idct Irq Enable Register416................................................................................................................................................................
Table 17-26 Dct/idct Irq Enable Register Description416................................................................................................................................................................
Dct/idct Irq Status Register417................................................................................................................................................................
Table 17-27 Dct/idct Irq Status Register Description417................................................................................................................................................................
Dct/idct Source Data Address418................................................................................................................................................................
Dct/idct Destination Data Address418................................................................................................................................................................
Table 17-28 Dct/idct Source Data Address Register Description418................................................................................................................................................................
Table 17-29 Dct/idct Destination Data Address Register Description418................................................................................................................................................................
Dct/idct X-offset Address419................................................................................................................................................................
Dct/idct Y-offset Address419................................................................................................................................................................
Table 17-30 Dct/idct X-offset Address Register Description419................................................................................................................................................................
Dct/idct Xy Count420................................................................................................................................................................
Table 17-31 Dct/idct Y-offset Address Register Description420................................................................................................................................................................
Table 17-32 Dct/idct Xy Count Register Description420................................................................................................................................................................
Dct/idct Skip Address421................................................................................................................................................................
Table 17-33 Dct/idct Skip Address Register Description421................................................................................................................................................................
Dct/idct Data Fifo422................................................................................................................................................................
Table 17-34 Dct/idct Data Fifo Register Description422................................................................................................................................................................
Spi Block Diagram423................................................................................................................................................................
Table 18-1 Spi 1 And Spi 2 Signal Multiplexing423................................................................................................................................................................
Phase And Polarity Configurations424................................................................................................................................................................
Figure 18-1 Spi Module Block Diagram424................................................................................................................................................................
Signals425................................................................................................................................................................
Pin Configuration For Spi 1 And Spi 2425................................................................................................................................................................
Figure 18-2 Spi Generic Timing425................................................................................................................................................................
Table 18-2 Spi Pin Configuration426................................................................................................................................................................
Table 18-3 Spi Module Register Memory Map427................................................................................................................................................................
Receive (rx) Data Registers428................................................................................................................................................................
Table 18-4 Spi 1 Rx Data Register And Spi 2 Rx Data Register Description428................................................................................................................................................................
Transmit (tx) Data Registers429................................................................................................................................................................
Table 18-5 Spi 1 Tx Data Register And Spi 2 Tx Data Register Description429................................................................................................................................................................
Control Registers430................................................................................................................................................................
Table 18-6 Spi 1 Control Register And Spi 2 Control Register Description430................................................................................................................................................................
Interrupt Control/status Registers432................................................................................................................................................................
And Spi 2 Interrupt Control/status Register Description433................................................................................................................................................................
Test Registers434................................................................................................................................................................
Table 18-8 Spi 1 Test Register And Spi 2 Test Register Description434................................................................................................................................................................
Sample Period Control Registers435................................................................................................................................................................
Dma Control Registers436................................................................................................................................................................
And Spi 2 Dma Control Register Description436................................................................................................................................................................
Soft Reset Registers437................................................................................................................................................................
Table 18-11 Spi 1 Soft Reset Register And Spi 2 Soft Reset Register Description437................................................................................................................................................................
Table 19-1 Supported Panel Characteristics439................................................................................................................................................................
Lcdc Operation440................................................................................................................................................................
Lcd Screen Format440................................................................................................................................................................
Figure 19-1 Lcdc Block Diagram440................................................................................................................................................................
Panning441................................................................................................................................................................
Display Data Mapping441................................................................................................................................................................
Figure 19-2 Lcd Screen Format441................................................................................................................................................................
Figure 19-3 Pixel Location On Display Screen442................................................................................................................................................................
Figure 19-4 Display Data Mapping, 1/2/4/8 Bpp Modes443................................................................................................................................................................
Table 19-2 Display Mapping In 12 Bpp, Cstn Panel, Little Endian444................................................................................................................................................................
Table 19-3 Display Mapping In 12 Bpp, Cstn Panel, Little Endian444................................................................................................................................................................
Black-and-white Operation445................................................................................................................................................................
Gray-scale Operation445................................................................................................................................................................
Figure 19-5 Display Data Mapping, 16 Bpp Mode445................................................................................................................................................................
Table 19-4 Display Mapping In 12 Bpp, Cstn Panel, Big Endian445................................................................................................................................................................
Color Generation446................................................................................................................................................................
Figure 19-6 Gray-scale Pixel Generation446................................................................................................................................................................
Figure 19-7 Passive Matrix Color Pixel Generation447................................................................................................................................................................
Figure 19-8 Active Matrix Color Pixel Generation447................................................................................................................................................................
Frame Rate Modulation Control (frc)448................................................................................................................................................................
Panel Interface Signals And Timing448................................................................................................................................................................
Table 19-5 Gray Palette Density448................................................................................................................................................................
Pin Configuration For Lcdc449................................................................................................................................................................
Figure 19-9 Lcdc Interface Signals449................................................................................................................................................................
Table 19-6 Pin Configuration449................................................................................................................................................................
Passive Matrix Panel Interface Signals450................................................................................................................................................................
Figure 19-10 Lcdc Interface Timing For 4-bit Data Width Gray-scale Panels450................................................................................................................................................................
Passive Panel Interface Timing451................................................................................................................................................................
Figure 19-11 Lcdc Interface Timing For 8-bit Data Passive Matrix Color Panels451................................................................................................................................................................
Bpp Mode Color Stn Panel452................................................................................................................................................................
Active Matrix Panel Interface Signals452................................................................................................................................................................
Figure 19-12 Horizontal Sync Pulse Timing In Passive Mode452................................................................................................................................................................
Figure 19-13 Vertical Sync Pulse Timing Passive, Color, (non-tft) Mode452................................................................................................................................................................
Table 19-7 Tft Color Channel Assignments453................................................................................................................................................................
Active Panel Interface Timing454................................................................................................................................................................
Figure 19-14 Lcdc Interface Timing For Active Matrix Color Panels454................................................................................................................................................................
Figure 19-15 Horizontal Sync Pulse Timing In Tft Mode455................................................................................................................................................................
Figure 19-16 Vertical Sync Pulse Timing Tft Mode455................................................................................................................................................................
Table 19-8 Lcdc Register Memory Map456................................................................................................................................................................
Figure 19-17 Register Memory Mapping Summary457................................................................................................................................................................
Screen Start Address Register458................................................................................................................................................................
Size Register458................................................................................................................................................................
Table 19-9 Screen Start Address Register Description458................................................................................................................................................................
Virtual Page Width Register459................................................................................................................................................................
Table 19-11 Virtual Page Width Register Description459................................................................................................................................................................
Table 19-10 Size Register Description459................................................................................................................................................................
Panel Configuration Register460................................................................................................................................................................
Table 19-12 Panel Configuration Register Description460................................................................................................................................................................
Horizontal Configuration Register462................................................................................................................................................................
Table 19-13 Horizontal Configuration Register Description462................................................................................................................................................................
Vertical Configuration Register463................................................................................................................................................................
Table 19-14 Vertical Configuration Register Description463................................................................................................................................................................
Panning Offset Register464................................................................................................................................................................
Table 19-15 Panning Offset Register Description464................................................................................................................................................................
Lcd Cursor Position Register465................................................................................................................................................................
Table 19-16 Lcd Cursor X Position Register Description465................................................................................................................................................................
Lcd Cursor Width Height And Blink Register466................................................................................................................................................................
Lcd Color Cursor Mapping Register466................................................................................................................................................................
Table 19-17 Lcd Cursor Width Height And Blink Register Description466................................................................................................................................................................
Table 19-18 Lcd Color Cursor Mapping Register Description467................................................................................................................................................................
Sharp Configuration 1 Register468................................................................................................................................................................
Table 19-19 Sharp Configuration 1 Register Description468................................................................................................................................................................
Figure 19-18 Horizontal Timing In Mc9328mx1469................................................................................................................................................................
Pwm Contrast Control Register470................................................................................................................................................................
Table 19-20 Pwm Contrast Control Register Description470................................................................................................................................................................
Refresh Mode Control Register471................................................................................................................................................................
Table 19-21 Refresh Mode Control Register Description471................................................................................................................................................................
Table 19-22 Dma Control Register Description472................................................................................................................................................................
Interrupt Configuration Register473................................................................................................................................................................
Table 19-23 Interrupt Configuration Register Description473................................................................................................................................................................
Interrupt Status Register474................................................................................................................................................................
Table 19-24 Interrupt Status Register Description474................................................................................................................................................................
Mapping Ram Registers475................................................................................................................................................................
One Bit/pixel Monochrome Mode475................................................................................................................................................................
Four Bits/pixel Gray-scale Mode475................................................................................................................................................................
Four Bits/pixel Passive Matrix Color Mode475................................................................................................................................................................
Table 19-25 Four Bits/pixel Gray-scale Mode475................................................................................................................................................................
Eight Bits/pixel Passive Matrix Color Mode476................................................................................................................................................................
Four Bits/pixel Active Matrix Color Mode476................................................................................................................................................................
Table 19-26 Four Bits/pixel Passive Matrix Color Mode476................................................................................................................................................................
Table 19-27 Eight Bits/pixel Passive Matrix Color Mode476................................................................................................................................................................
Eight Bits/pixel Active Matrix Color Mode477................................................................................................................................................................
Twelve Bits/pixel And Sixteen Bits/pixel Active Matrix Color Mode477................................................................................................................................................................
Table 19-28 Four Bits/pixel Active Matrix Color Mode477................................................................................................................................................................
Table 19-29 Eight Bits/pixel Active Matrix Color Mode477................................................................................................................................................................
Mmc/sd Module Block Diagram480................................................................................................................................................................
Figure 20-1 Mmc/sd Module Block Diagram480................................................................................................................................................................
Figure 20-2 System Interconnection With Mmc/sd Module480................................................................................................................................................................
Mmc/sd Module And Card Information481................................................................................................................................................................
Mmc And Sd Card Pin Assignments And Registers481................................................................................................................................................................
Table 20-1 Mmc/sd Card Pin Assignment481................................................................................................................................................................
Table 20-2 Mmc/sd Card Registers481................................................................................................................................................................
Communication482................................................................................................................................................................
Pin Configuration For The Mmc/sd Module483................................................................................................................................................................
Functional Description483................................................................................................................................................................
Table 20-3 Pin Configuration483................................................................................................................................................................
Dma Interface484................................................................................................................................................................
Figure 20-3 Dmac Interface Block Diagram484................................................................................................................................................................
Dma Burst Request485................................................................................................................................................................
Write-error Detection486................................................................................................................................................................
Memory Controller (register Handler)486................................................................................................................................................................
Figure 20-4 Fifo Usage For Different Modes486................................................................................................................................................................
Sd I/o—irq And Readwait Service Handling487................................................................................................................................................................
Card Detection487................................................................................................................................................................
Figure 20-5 Memory Controller Block Diagram487................................................................................................................................................................
Mmc/sd Module Interrupt Handling488................................................................................................................................................................
Logic And Command Interpreters488................................................................................................................................................................
Figure 20-6 Card Detection Mechanism488................................................................................................................................................................
Figure 20-7 Block Diagram For Logic And Command Interpreters489................................................................................................................................................................
System Clock Controller490................................................................................................................................................................
Figure 20-8 Command Crc Shift Register (sd_dat Has A Similar Structure)490................................................................................................................................................................
Figure 20-9 Clock Tree For The Mmc/sd Module490................................................................................................................................................................
Card Clock Control491................................................................................................................................................................
Figure 20-10 System Clock Control Unit491................................................................................................................................................................
Table 20-4 Multimedia Controller Register Memory Map491................................................................................................................................................................
Mmc/sd Clock Control Register492................................................................................................................................................................
Table 20-5 Mmc/sd Clock Control Register Description493................................................................................................................................................................
Mmc/sd Status Register494................................................................................................................................................................
Table 20-6 Mmc/sd Status Register Description494................................................................................................................................................................
Mmc/sd Clock Rate Register497................................................................................................................................................................
Table 20-7 Mmc/sd Clock Rate Register Description497................................................................................................................................................................
Mmc/sd Command And Data Control Register498................................................................................................................................................................
Table 20-8 Mmc/sd Command And Data Control Register Description498................................................................................................................................................................
Mmc/sd Response Time-out Register499................................................................................................................................................................
Mmc/sd Read Time-out Register500................................................................................................................................................................
Table 20-9 Mmc/sd Response Time-out Register Description500................................................................................................................................................................
Table 20-10 Mmc/sd Read Time-out Register Description500................................................................................................................................................................
Mmc/sd Block Length Register501................................................................................................................................................................
Table 20-11 Mmc/sd Block Length Register Description501................................................................................................................................................................
Mmc/sd Number Of Blocks Register502................................................................................................................................................................
Table 20-12 Mmc/sd Number Of Blocks Register Description502................................................................................................................................................................
Mmc/sd Revision Number Register503................................................................................................................................................................
Table 20-13 Mmc/sd Revision Number Register Description503................................................................................................................................................................
Mmc/sd Interrupt Mask Register504................................................................................................................................................................
Table 20-14 Mmc/sd Interrupt Mask Register Description504................................................................................................................................................................
Table 20-15 Interrupt Mechanisms505................................................................................................................................................................
Commands And Arguments506................................................................................................................................................................
Mmc/sd Command Number Register507................................................................................................................................................................
Mmc/sd Higher Argument Register507................................................................................................................................................................
Table 20-16 Mmc/sd Command Number Register Description507................................................................................................................................................................
Mmc/sd Lower Argument Register508................................................................................................................................................................
Table 20-17 Mmc/sd Higher Argument Register Description508................................................................................................................................................................
Table 20-18 Mmc/sd Lower Argument Register Description508................................................................................................................................................................
Mmc/sd Response Fifo Register509................................................................................................................................................................
Table 20-19 Mmc/sd Response Fifo Register Description509................................................................................................................................................................
Mmc/sd Buffer Access Register510................................................................................................................................................................
Functional Example For The Mmc/sd Module510................................................................................................................................................................
Table 20-20 Mmc/sd Buffer Access Register Description510................................................................................................................................................................
Basic Operation511................................................................................................................................................................
Card Identification State511................................................................................................................................................................
Card Detect511................................................................................................................................................................
Reset512................................................................................................................................................................
Voltage Validation512................................................................................................................................................................
Card Registry513................................................................................................................................................................
Card Access515................................................................................................................................................................
Block Access—block Write And Block Read515................................................................................................................................................................
Block Write515................................................................................................................................................................
Block Read517................................................................................................................................................................
Stream Access—stream Write And Stream Read (mmc Only)520................................................................................................................................................................
Stream Write520................................................................................................................................................................
Stream Read521................................................................................................................................................................
Erase—group Erase And Sector Erase (mmc Only)522................................................................................................................................................................
Wide Bus Selection Or Deselection523................................................................................................................................................................
Protection Management523................................................................................................................................................................
Card Internal Write Protection523................................................................................................................................................................
Mechanical Write Protect Switch524................................................................................................................................................................
Password Protect524................................................................................................................................................................
Table 20-21 Structure Of Command Data Block524................................................................................................................................................................
Setting The Password525................................................................................................................................................................
Resetting The Password525................................................................................................................................................................
Locking A Card525................................................................................................................................................................
Unlocking The Card526................................................................................................................................................................
Forcing Erase526................................................................................................................................................................
Card Status Register527................................................................................................................................................................
Table 20-22 Card Status Register Description527................................................................................................................................................................
Sd Status Register529................................................................................................................................................................
Sd I/o530................................................................................................................................................................
Sd I/o Interrupts530................................................................................................................................................................
Table 20-23 Sd Status Register530................................................................................................................................................................
Sd I/o Suspend And Resume531................................................................................................................................................................
Sd I/o Readwait531................................................................................................................................................................
Commands And Responses532................................................................................................................................................................
Application-specific And General Commands533................................................................................................................................................................
Command Types533................................................................................................................................................................
Command Formats533................................................................................................................................................................
Commands For The Mmc/sd Module534................................................................................................................................................................
Table 20-24 Command Format534................................................................................................................................................................
Table 20-25 Commands For Mmc/sd Module534................................................................................................................................................................
Response Formats538................................................................................................................................................................
R1—normal Response538................................................................................................................................................................
R1b—normal Response With Busy539................................................................................................................................................................
R2—cid, Csd Register539................................................................................................................................................................
R3—ocr Register539................................................................................................................................................................
R4—fast I/o For Mmc Only539................................................................................................................................................................
Table 20-26 R1 Response539................................................................................................................................................................
Table 20-27 R2 Response539................................................................................................................................................................
Table 20-28 R3 Response539................................................................................................................................................................
R4b—sd I/o Only540................................................................................................................................................................
R5—interrupt Request (for Mmc Only)540................................................................................................................................................................
R6—sd I/o Only540................................................................................................................................................................
Table 20-29 R4 Response540................................................................................................................................................................
Table 20-30 R4b Response540................................................................................................................................................................
Table 20-31 R5 Response540................................................................................................................................................................
Table 20-32 R6 Response541................................................................................................................................................................
Block Diagram And Description543................................................................................................................................................................
Memory Stick Interface544................................................................................................................................................................
Figure 21-1 Memory Stick Host Controller Simplified Block Diagram544................................................................................................................................................................
Pin Configuration For The Mshc Module545................................................................................................................................................................
Figure 21-2 Memory Stick Interface545................................................................................................................................................................
Memory Stick Host Controller Operation546................................................................................................................................................................
Data Fifo Operation546................................................................................................................................................................
Table 21-1 Pin Configuration546................................................................................................................................................................
Bus State Control Operation547................................................................................................................................................................
Mshc Module Interrupt Operation547................................................................................................................................................................
Interrupt Sources547................................................................................................................................................................
Table 21-2 Mshc Module Interrupt Sources Summary547................................................................................................................................................................
Sdio Interrupt Operation548................................................................................................................................................................
Figure 21-3 Memory Stick Interrupt Transfer State (bs0) Operation548................................................................................................................................................................
Reset Operation549................................................................................................................................................................
Power Save Mode Operation550................................................................................................................................................................
Figure 21-4 Power Save Mode550................................................................................................................................................................
Table 21-3 Interrupt Detect Capability On Power Save Mode550................................................................................................................................................................
Register Access During Power Save Mode551................................................................................................................................................................
Register Access When Mshc Module Is Disabled551................................................................................................................................................................
Auto Command Function551................................................................................................................................................................
Figure 21-5 Auto Command Function Operation552................................................................................................................................................................
Serial Clock Divider Operation553................................................................................................................................................................
System-level Dma Transfer Operation553................................................................................................................................................................
Figure 21-6 Mshc Module Serial Clock Divider553................................................................................................................................................................
Table 21-4 Serial Clock Divider Settings553................................................................................................................................................................
Table 21-5 Mshc Module Dma Configuration Options554................................................................................................................................................................
Table 21-6 Mshc Module Register Memory Map554................................................................................................................................................................
Memory Stick Command Register555................................................................................................................................................................
Table 21-7 Memory Stick Command Register Description555................................................................................................................................................................
Memory Stick Control/status Register556................................................................................................................................................................
Table 21-8 Memory Stick Control/status Register Description556................................................................................................................................................................
Memory Stick Transmit Fifo Data Register557................................................................................................................................................................
Memory Stick Receive Fifo Data Register558................................................................................................................................................................
Table 21-9 Memory Stick Transmit Fifo Data Register Description558................................................................................................................................................................
Memory Stick Interrupt Control/status Register559................................................................................................................................................................
Table 21-10 Memory Stick Receive Fifo Data Register Description559................................................................................................................................................................
Table 21-11 Memory Stick Interrupt Control/status Register Description559................................................................................................................................................................
Memory Stick Parallel Port Control/data Register561................................................................................................................................................................
Table 21-12 Memory Stick Parallel Port Control/data Register Description561................................................................................................................................................................
Memory Stick Control 2 Register562................................................................................................................................................................
Table 21-13 Memory Stick Control 2 Register Description562................................................................................................................................................................
Memory Stick Auto Command Register563................................................................................................................................................................
Memory Stick Fifo Access Error Control/status Register563................................................................................................................................................................
Table 21-14 Memory Stick Auto Command Register Description563................................................................................................................................................................
Memory Stick Serial Clock Divider Register564................................................................................................................................................................
Table 21-15 Memory Stick Fifo Access Error Control/status Register Description564................................................................................................................................................................
Memory Stick Dma Request Control Register565................................................................................................................................................................
Table 21-16 Memory Stick Serial Clock Divider Register Description565................................................................................................................................................................
Programmer's Reference566................................................................................................................................................................
Memory Stick Serial Interface Overview566................................................................................................................................................................
Table 21-17 Memory Stick Dma Request Control Register Description566................................................................................................................................................................
Figure 21-7 Memory Stick Bus Four State Access Protocol567................................................................................................................................................................
Table 21-18 Serial Interface Signal Specifications567................................................................................................................................................................
Table 21-19 Four State Access Mode567................................................................................................................................................................
Protocol568................................................................................................................................................................
Write Packet568................................................................................................................................................................
Read Packet568................................................................................................................................................................
Figure 21-8 Write Packet568................................................................................................................................................................
Figure 21-9 Read Packet568................................................................................................................................................................
Table 21-20 Write Packet568................................................................................................................................................................
Transfer Protocol Command (tpc)569................................................................................................................................................................
Table 21-21 Read Packet569................................................................................................................................................................
Table 21-22 Tpc Code Specification569................................................................................................................................................................
Protocol Error570................................................................................................................................................................
Figure 21-10 Two State Access Mode570................................................................................................................................................................
Figure 21-11 Write Packet Time-out571................................................................................................................................................................
Figure 21-12 Read Packet Time-out571................................................................................................................................................................
Table 21-23 Bus State In Two State Access Mode571................................................................................................................................................................
Two State Access Mode Factor572................................................................................................................................................................
Signal Timing572................................................................................................................................................................
Timing572................................................................................................................................................................
Figure 21-13 Signal Timing572................................................................................................................................................................
Table 21-24 Two State Access Mode Factor572................................................................................................................................................................
Bus State Extension573................................................................................................................................................................
Data Transfer Extension573................................................................................................................................................................
Figure 21-14 Bus State Extension573................................................................................................................................................................
Figure 21-15 Sclk Extension For Data Wait573................................................................................................................................................................
Pwm Signals575................................................................................................................................................................
Clock Signals575................................................................................................................................................................
Figure 22-1 Pulse-width Modulator Block Diagram575................................................................................................................................................................
Pin Configuration For Pwm576................................................................................................................................................................
Pwm Operation576................................................................................................................................................................
Playback Mode576................................................................................................................................................................
Figure 22-2 Audio Waveform Generation576................................................................................................................................................................
Table 22-1 Pin Configuration576................................................................................................................................................................
Tone Mode577................................................................................................................................................................
Digital-to-analog Converter (d/a) Mode577................................................................................................................................................................
Pwm Control Register577................................................................................................................................................................
Table 22-2 Pwm Module Register Memory Map577................................................................................................................................................................
Table 22-3 Pwm Control Register Description578................................................................................................................................................................
Hctr And Bctr Bit Description579................................................................................................................................................................
Pwm Sample Register580................................................................................................................................................................
Table 22-4 Hctr And Bctr Bit Swapping580................................................................................................................................................................
Table 22-5 Pwm Sample Register Description580................................................................................................................................................................
Pwm Period Register581................................................................................................................................................................
Table 22-6 Pwm Period Register Description581................................................................................................................................................................
Pwm Counter Register582................................................................................................................................................................
Table 22-7 Pwm Counter Register Description582................................................................................................................................................................
Prescaler And Counter584................................................................................................................................................................
Figure 23-1 Real-time Clock Block Diagram584................................................................................................................................................................
Alarm585................................................................................................................................................................
Sampling Timer585................................................................................................................................................................
Minute Stopwatch585................................................................................................................................................................
Table 23-1 Sampling Timer Frequencies585................................................................................................................................................................
Rtc Days Counter Register586................................................................................................................................................................
Table 23-2 Rtc Module Register Memory Map586................................................................................................................................................................
Rtc Hours And Minutes Counter Register587................................................................................................................................................................
Table 23-3 Rtc Days Counter Register Description587................................................................................................................................................................
Table 23-4 Rtc Hours And Minutes Counter Register Description587................................................................................................................................................................
Rtc Seconds Counter Register588................................................................................................................................................................
Table 23-5 Rtc Seconds Counter Register Description588................................................................................................................................................................
Rtc Day Alarm Register589................................................................................................................................................................
Table 23-6 Rtc Day Alarm Register Description589................................................................................................................................................................
Rtc Hours And Minutes Alarm Register590................................................................................................................................................................
Table 23-7 Rtc Hours And Minutes Alarm Register Description590................................................................................................................................................................
Rtc Seconds Alarm Register591................................................................................................................................................................
Table 23-8 Rtc Seconds Alarm Register Description591................................................................................................................................................................
Rtc Control Register592................................................................................................................................................................
Rtc Interrupt Status Register592................................................................................................................................................................
Table 23-9 Rtc Control Register Description592................................................................................................................................................................
Table 23-10 Rtc Interrupt Status Register Description593................................................................................................................................................................
Rtc Interrupt Enable Register595................................................................................................................................................................
Table 23-11 Rtc Interrupt Enable Register Description595................................................................................................................................................................
Stopwatch Minutes Register597................................................................................................................................................................
Table 23-12 Stopwatch Minutes Register Description597................................................................................................................................................................
Figure 24-1 Sdram Controller Block Diagram600................................................................................................................................................................
Functional Overview601................................................................................................................................................................
Sdram Command Controller601................................................................................................................................................................
Page And Bank Address Comparators601................................................................................................................................................................
Row And Column Address Multiplexer601................................................................................................................................................................
Data Aligner And Multiplexer601................................................................................................................................................................
Configuration Registers601................................................................................................................................................................
Refresh Request Counter601................................................................................................................................................................
Powerdown Timer602................................................................................................................................................................
Dma Operation With The Sdram Controller602................................................................................................................................................................
External Interface602................................................................................................................................................................
Table 24-1 Ahb Bus And Internal Interface Signals602................................................................................................................................................................
Table 24-2 Sdram Interface Pin Characteristics602................................................................................................................................................................
Sdclk—sdram Clock603................................................................................................................................................................
Sdcke0, Sdcke1—sdram Clock Enables603................................................................................................................................................................
Csd0, Csd1—sdram Chip-select603................................................................................................................................................................
Dq [31:0]—data Bus (internal)604................................................................................................................................................................
Ma [11:0]—multiplexed Address Bus604................................................................................................................................................................
Sdba [4:0], Sdiba [3:0]—non-multiplexed Address Bus604................................................................................................................................................................
Dqm3, Dqm2, Dqm1, Dqm0—data Qualifier Mask604................................................................................................................................................................
Sdwe—write Enable604................................................................................................................................................................
Ras—row Address Strobe604................................................................................................................................................................
Cas—column Address Strobe605................................................................................................................................................................
Reset_sf—reset Or Powerdown605................................................................................................................................................................
Pin Configuration For Sdramc605................................................................................................................................................................
Table 24-4 Pin Configuration605................................................................................................................................................................
Table 24-5 Sdram Module Register Memory Map606................................................................................................................................................................
Table 24-6 Sdram Array Memory Map606................................................................................................................................................................
Sdram Control Registers607................................................................................................................................................................
Table 24-7 Sdram 0 Control Register And Sdram 1 Control Register Description607................................................................................................................................................................
Figure 24-2 Memory Bank Interleaving Options611................................................................................................................................................................
Table 24-8 Settings For Srefr Field611................................................................................................................................................................
Figure 24-3 Cas Latency Timing612................................................................................................................................................................
Figure 24-4 Precharge Delay Timing613................................................................................................................................................................
Figure 24-5 Row-to-column Delay Timing613................................................................................................................................................................
Sdram Reset Register614................................................................................................................................................................
Figure 24-6 Row Cycle Timing614................................................................................................................................................................
Table 24-9 Sdram Reset Register Description614................................................................................................................................................................
Miscellaneous Register615................................................................................................................................................................
Table 24-10 Miscellaneous Register Description615................................................................................................................................................................
Operating Modes616................................................................................................................................................................
Sdram And Syncflash Command Encoding616................................................................................................................................................................
Table 24-11 Sdram And Syncflash Command Encoding616................................................................................................................................................................
Normal Read/write Mode (smode = 000)617................................................................................................................................................................
Figure 24-7 Off-page Single Read Timing Diagram (32-bit Memory)618................................................................................................................................................................
Figure 24-8 On-page Single Read Timing Diagram (32-bit Memory)618................................................................................................................................................................
Figure 24-9 Off-page Burst Read Timing Diagram (32-bit Memory)619................................................................................................................................................................
Figure 24-10 On-page Burst Read Timing Diagram (32-bit Memory)619................................................................................................................................................................
Figure 24-11 Off-page Write Followed By On-page Write Timing Diagram619................................................................................................................................................................
Figure 24-12 Off-page Burst Write Timing Diagram620................................................................................................................................................................
Figure 24-13 On-page Burst Write Timing Diagram620................................................................................................................................................................
Figure 24-14 Single Write Followed By On-page Read Timing Diagram620................................................................................................................................................................
Precharge Command Mode (smode = 001)621................................................................................................................................................................
Figure 24-15 Burst Write Followed By On-page Read Timing Diagram621................................................................................................................................................................
Figure 24-16 Single Read Followed By On-page Write Timing Diagram621................................................................................................................................................................
Figure 24-17 Burst Read Followed By On-page Write Timing Diagram621................................................................................................................................................................
Auto-refresh Mode (smode = 010)622................................................................................................................................................................
Figure 24-18 Precharge Bank Timing Diagram622................................................................................................................................................................
Figure 24-19 Precharge All Timing Diagram622................................................................................................................................................................
Set Mode Register Mode (smode = 011)623................................................................................................................................................................
Figure 24-20 Software Initiated Auto-refresh Timing Diagram623................................................................................................................................................................
Syncflash Load Command Mode624................................................................................................................................................................
Figure 24-21 Set Mode Register State Diagram624................................................................................................................................................................
Figure 24-22 Set Mode Register Timing Diagram624................................................................................................................................................................
Syncflash Program Mode625................................................................................................................................................................
Figure 24-23 Load Command Register Timing Diagram625................................................................................................................................................................
Figure 24-24 Syncflash Program Mode State Diagram625................................................................................................................................................................
General Operation626................................................................................................................................................................
Figure 24-25 Syncflash Program Timing Diagram626................................................................................................................................................................
Figure 24-26 Syncflash Read Status Register Timing Diagram626................................................................................................................................................................
Address Multiplexing627................................................................................................................................................................
Multiplexed Address Bus627................................................................................................................................................................
Table 24-12 Jedec Standard Single Data Rate Sdrams627................................................................................................................................................................
Table 24-13 Address Multiplexing By Column Width628................................................................................................................................................................
Table 24-14 Mc9328mx1 To Sdram Interface Connections628................................................................................................................................................................
Non-multiplexed Address Bus629................................................................................................................................................................
Bank Addresses630................................................................................................................................................................
Refresh630................................................................................................................................................................
Figure 24-27 Hardware Refresh Timing Diagram630................................................................................................................................................................
Self-refresh631................................................................................................................................................................
Self-refresh During Reset_in631................................................................................................................................................................
Self-refresh During Low-power Mode631................................................................................................................................................................
Powerdown Operation During Reset And Low-power Modes631................................................................................................................................................................
Figure 24-28 Hardware Refresh With Pending Bus Cycle Timing Diagram631................................................................................................................................................................
Figure 24-29 Self-refresh Entry Due To Low-power Mode Timing Diagram632................................................................................................................................................................
Figure 24-30 Low-power Mode Self-refresh Exit Timing Diagram632................................................................................................................................................................
Clock Suspend Low-power Mode633................................................................................................................................................................
Powerdown633................................................................................................................................................................
Figure 24-31 Powerdown Mode Resulting From Reset With Refresh Disabled633................................................................................................................................................................
Clock Suspend634................................................................................................................................................................
Refresh During Powerdown Or Clock Suspend634................................................................................................................................................................
Figure 24-32 Powerdown Mode Entry Timing Diagram634................................................................................................................................................................
Figure 24-33 Powerdown Exit Timing Diagram634................................................................................................................................................................
Sdram Operation635................................................................................................................................................................
Sdram Selection635................................................................................................................................................................
Configuring Controller For Sdram Memory Array635................................................................................................................................................................
Figure 24-34 Clock Suspend Timing Diagram635................................................................................................................................................................
Cas Latency636................................................................................................................................................................
Row Precharge Delay636................................................................................................................................................................
Row-to-column Delay636................................................................................................................................................................
Row Cycle Delay636................................................................................................................................................................
Refresh Rate636................................................................................................................................................................
Memory Configuration Examples637................................................................................................................................................................
Figure 24-35 Single 64 Mbit (4m X 16) Connection Diagram (iam = 1)637................................................................................................................................................................
Table 24-15 Single 4m X 16 Control Register Values637................................................................................................................................................................
Figure 24-36 Single 64 Mbit (4m X 16 X 1) Connection Diagram (iam = 0)638................................................................................................................................................................
Table 24-16 Single 4m X 16 Control Register Values638................................................................................................................................................................
Figure 24-37 Single 128 Mbit (8m X 16) Connection Diagram (iam = 1)639................................................................................................................................................................
Table 24-17 Single 8m X 16 Control Register Values639................................................................................................................................................................
Figure 24-38 Single 128 Mbit (8m X 16) Connection Diagram (iam = 0)640................................................................................................................................................................
Table 24-18 Single 8m X 16 Control Register Values640................................................................................................................................................................
Figure 24-39 Single 256 Mbit (16m X 16) Connection Diagram (iam = 1)641................................................................................................................................................................
Table 24-19 Single 16m X16 Control Register Values641................................................................................................................................................................
Figure 24-40 Single 256 Mbit (16m X 16) Connection Diagram (iam = 1)642................................................................................................................................................................
Table 24-20 Single 16m X16 Control Register Values642................................................................................................................................................................
Figure 24-41 Dual 64 Mbit (4m X 16 X 2) Connection Diagram (iam = 1)643................................................................................................................................................................
Table 24-21 Dual 64 Mbit (4m X 16 X 2) Control Register Values (iam = 1)643................................................................................................................................................................
Figure 24-42 Dual 64 Mbit (4m X 16 X 2) Connection Diagram (iam = 0)644................................................................................................................................................................
Table 24-22 Dual 64 Mbit (4m X 16 X 2) Control Register Values (iam = 0)644................................................................................................................................................................
Figure 24-43 Dual 128 Mbit (8m X 16 X 2) Connection Diagram (iam = 1)645................................................................................................................................................................
Table 24-23 Dual 128 Mbit (8m X 16 X 2) Control Register Values (iam = 1)645................................................................................................................................................................
Figure 24-44 Dual 128 Mbit (8m X 16 X 2) Connection Diagram (iam = 0)646................................................................................................................................................................
Table 24-24 Dual 128 Mbit (8m X 16 X 2) Control Register Values (iam = 0)646................................................................................................................................................................
Figure 24-45 Dual 256 Mbit (16m X 16 X 2) Connection Diagram (iam = 1)647................................................................................................................................................................
Table 24-25 Dual 256 Mbit (16m X 16 X 2) Control Register Values (iam = 1)647................................................................................................................................................................
Figure 24-46 Dual 256 Mbit (16m X 16 X 2) Connection Diagram (iam = 0)648................................................................................................................................................................
Table 24-26 Dual 256 Mbit (16m X 16 X 2) Control Register Values (iam = 0)648................................................................................................................................................................
Figure 24-47 Single 64 Mbit (2m X 32) Connection Diagram (iam = 1)649................................................................................................................................................................
Table 24-27 Single 64 Mbit (2m X 32) Control Register Values (iam = 1)649................................................................................................................................................................
Figure 24-48 Single 64 Mbit (2m X 32) Connection Diagram (iam = 0)650................................................................................................................................................................
Table 24-28 Single 64 Mbit (2m X 32) Control Register Values650................................................................................................................................................................
Figure 24-49 Single 128 Mbit (4m X 32) Connection Diagram (iam = 1)651................................................................................................................................................................
Table 24-29 Single 128 Mbit (4m X 32) Control Register Values (iam = 1)651................................................................................................................................................................
Figure 24-50 Single 128 Mbit (4m X 32) Connection Diagram (iam = 0)652................................................................................................................................................................
Table 24-30 Single 128 Mbit (4m X 32) Control Register Values (iam = 0)652................................................................................................................................................................
Figure 24-51 Single 256 Mbit (8m X 32) Connection Diagram (iam = 1)653................................................................................................................................................................
Table 24-31 Single 256 Mbit (8m X 32) Control Register Values (iam = 1)653................................................................................................................................................................
Sdram Reset Initialization654................................................................................................................................................................
Figure 24-52 Single 256 Mbit (8m X 32) Connection Diagram (iam = 0)654................................................................................................................................................................
Table 24-32 Single 256 Mbit (8m X 32) Control Register Values (iam = 0)654................................................................................................................................................................
Figure 24-53 Sdram Power-on Initialization Sequence655................................................................................................................................................................
Mode Register Programming656................................................................................................................................................................
Table 24-33 4m X 16 Memory Configuration656................................................................................................................................................................
Table 24-34 8m X 16 Memory Configuration657................................................................................................................................................................
Table 24-35 16m X 16 Memory Configuration657................................................................................................................................................................
Table 24-36 2m X 32 Memory Configuration657................................................................................................................................................................
Table 24-37 4m X 32 Memory Configuration657................................................................................................................................................................
Table 24-38 8m X 32 Memory Configuration657................................................................................................................................................................
Table 24-39 Mc9328mx1 Sdram Memory Configuration658................................................................................................................................................................
Mode Register Programming Examples659................................................................................................................................................................
Example 1—256 Mbit Sdram Mode Register659................................................................................................................................................................
Table 24-40 256 Mbit Sdram Mode Register659................................................................................................................................................................
Table 24-41 256 Mbit Sdram Mode Register Description659................................................................................................................................................................
Table 24-42 256 Mbit Sdram Mode Register With Values660................................................................................................................................................................
Table 24-43 Mc9328mx1 Address Calculation For Given Mode Register Values660................................................................................................................................................................
Example 2—64 Mbit Sdram Mode Register661................................................................................................................................................................
Table 24-44 64 Mbit Sdram Mode Register661................................................................................................................................................................
Table 24-45 64 Mbit Sdram Mode Register Description661................................................................................................................................................................
Table 24-46 64 Mbit Sdram Mode Register With Values662................................................................................................................................................................
Table 24-47 Mc9328mx1 Address Calculation For Given Mode Register Value662................................................................................................................................................................
Sdram Memory Refresh663................................................................................................................................................................
Syncflash Operation663................................................................................................................................................................
Syncflash Reset Initialization663................................................................................................................................................................
Table 24-48 Sdram Memory Refresh663................................................................................................................................................................
Syncflash Mode Register Programming664................................................................................................................................................................
Booting From Syncflash664................................................................................................................................................................
Syncflash Configuration664................................................................................................................................................................
Figure 24-54 Sync Flash Reset Timing664................................................................................................................................................................
Figure 24-55 Single 64 Mbit Syncflash Connection Diagram (iam = 0)665................................................................................................................................................................
Table 24-49 Single 4m X 16 Syncflash Control Register Values665................................................................................................................................................................
Table 24-50 Dual 4m X 16 Syncflash Control Register Values (iam = 0)665................................................................................................................................................................
Syncflash Programming666................................................................................................................................................................
Figure 24-56 Dual 64 Mbit Syncflash Connection Diagram (iam = 0)666................................................................................................................................................................
Clock Suspend Timer Use With Syncflash667................................................................................................................................................................
Table 24-51 Syncflash Command Sequences667................................................................................................................................................................
Powerdown Operation With Syncflash668................................................................................................................................................................
Deep Powerdown Operation With Syncflash668................................................................................................................................................................
Figure 24-57 Syncflash Clock Suspend Timer Operation Timing Diagram668................................................................................................................................................................
Figure 24-58 Syncflash Powerdown Operation Timing Diagram668................................................................................................................................................................
Figure 24-59 Syncflash Deep Powerdown Operation Timing Diagram669................................................................................................................................................................
Module Overview671................................................................................................................................................................
Figure 25-1 Sim Simplified Block Diagram671................................................................................................................................................................
Sim Clock Generator672................................................................................................................................................................
Sim Transmitter672................................................................................................................................................................
Sim Receiver672................................................................................................................................................................
Table 25-1 Sim Transmitter Interrupt Summary672................................................................................................................................................................
Sim Port Control673................................................................................................................................................................
Sim General Purpose Counter673................................................................................................................................................................
Sim Lrc And Crc673................................................................................................................................................................
Table 25-2 Sim Receiver Interrupt Summary673................................................................................................................................................................
Table 25-3 Sim Port Control Interrupt Summary673................................................................................................................................................................
Table 25-4 Sim Port Control Interrupt Summary673................................................................................................................................................................
Baud Clock Generation674................................................................................................................................................................
Figure 25-2 Sim Clock Generator Diagram674................................................................................................................................................................
Transmitter Clock Generation675................................................................................................................................................................
Receiver Clock Generation675................................................................................................................................................................
Port Controller Clock Generation675................................................................................................................................................................
Transmit State Machine675................................................................................................................................................................
Figure 25-3 Transmit State Machine Operation Diagram676................................................................................................................................................................
Transmit Shift Register677................................................................................................................................................................
Transmit Fifo677................................................................................................................................................................
Transmit Guard Time Generator677................................................................................................................................................................
Transmit Nack Generator678................................................................................................................................................................
Figure 25-4 Transmit Guard Time Diagram678................................................................................................................................................................
Figure 25-5 Transmit Nack Operation678................................................................................................................................................................
Transmit Data Convention Logic679................................................................................................................................................................
Receive State Machine679................................................................................................................................................................
Figure 25-6 Sim Data Conventions679................................................................................................................................................................
Data Sampling / Voting681................................................................................................................................................................
Start Bit Detection681................................................................................................................................................................
Parity Error Detection681................................................................................................................................................................
Figure 25-7 Receive State Machine Diagram681................................................................................................................................................................
Figure 25-8 Start Bit Diagram681................................................................................................................................................................
Framing Error Detection682................................................................................................................................................................
Nack Detection682................................................................................................................................................................
Figure 25-9 Parity Bit Diagram682................................................................................................................................................................
Figure 25-10 Framing Error Diagram682................................................................................................................................................................
Initial Character Detection683................................................................................................................................................................
Receive Fifo683................................................................................................................................................................
Figure 25-11 Valid Initial Characters683................................................................................................................................................................
Figure 25-12 Inverse Convention Vs. Direct Convention683................................................................................................................................................................
Overrun Detection684................................................................................................................................................................
Character Wait Time Counter684................................................................................................................................................................
Sim Port Controller684................................................................................................................................................................
Smartcard Interface684................................................................................................................................................................
Smartcard Presence Detect685................................................................................................................................................................
Smartcard Automatic Powerdown685................................................................................................................................................................
Figure 25-13 Two Methods Of Smartcard Hookup To Mc9328mx1 Sim Port685................................................................................................................................................................
Sim Lrc Block686................................................................................................................................................................
Figure 25-14 Automatic Powerdown Sequence686................................................................................................................................................................
Sim Crc Block687................................................................................................................................................................
Figure 25-15 Cyclic Redundancy Check Circuit Diagram687................................................................................................................................................................
Sim Interrupts688................................................................................................................................................................
Pin Configuration For Sim688................................................................................................................................................................
Table 25-5 Sim Interrupts688................................................................................................................................................................
Table 25-6 Pin Configuration689................................................................................................................................................................
Table 25-7 Ssi Module Register Memory Map689................................................................................................................................................................
Table 25-8 Register Field Summary690................................................................................................................................................................
Port Control Register692................................................................................................................................................................
Table 25-9 Port Control Register Descriptions692................................................................................................................................................................
Control Register693................................................................................................................................................................
Table 25-10 Control Register Descriptions693................................................................................................................................................................
Receive Threshold Register695................................................................................................................................................................
Transmit/receive Enable Register696................................................................................................................................................................
Table 25-11 Receive Threshold Register Description696................................................................................................................................................................
Table 25-12 Transmit/receive Enable Register Description696................................................................................................................................................................
Transmit Status Register697................................................................................................................................................................
Table 25-13 Transmit Status Register Description697................................................................................................................................................................
Receive Status Register699................................................................................................................................................................
Table 25-14 Receive Status Register Description699................................................................................................................................................................
Interrupt Mask Register701................................................................................................................................................................
Table 25-15 Interrupt Mask Register Description701................................................................................................................................................................
Port Transmit Buffer Register702................................................................................................................................................................
Table 25-16 Port Transmit Buffer Register Description702................................................................................................................................................................
Receive Buffer Register703................................................................................................................................................................
Table 25-17 Receive Buffer Register Description703................................................................................................................................................................
Port Detect Register704................................................................................................................................................................
Table 25-18 Port Detect Register Description704................................................................................................................................................................
Transmit Threshold Register705................................................................................................................................................................
Table 25-19 Transmit Threshold Register Description705................................................................................................................................................................
Transmit Guard Control Register706................................................................................................................................................................
Table 25-20 Transmit Guard Control Register Description706................................................................................................................................................................
Open-drain Configuration Control Register707................................................................................................................................................................
Table 25-21 Open-drain Configuration Control Register Description707................................................................................................................................................................
Reset Control Register708................................................................................................................................................................
Table 25-22 Reset Control Register Description708................................................................................................................................................................
Character Wait Timer Register709................................................................................................................................................................
Table 25-23 Character Wait Timer Register Description709................................................................................................................................................................
General Purpose Counter Register710................................................................................................................................................................
Table 25-24 General Purpose Counter Register Description710................................................................................................................................................................
Divisor Register711................................................................................................................................................................
Functional Programming Example711................................................................................................................................................................
Configuring The Sim For Operation711................................................................................................................................................................
Table 25-25 Divisor Register Description711................................................................................................................................................................
Table 25-26 Configuring The Sim For Operation711................................................................................................................................................................
Configuring The Sim Receiver712................................................................................................................................................................
Table 25-27 Configuring The Sim Receiver712................................................................................................................................................................
Configuring The Sim Transmitter713................................................................................................................................................................
Table 25-28 Configuring The Sim Transmitter713................................................................................................................................................................
Configuring The Sim General Purpose Counter714................................................................................................................................................................
Configuring The Sim Linear Redundancy Check Block714................................................................................................................................................................
Table 25-29 Configuring The Sim General Purpose Counter714................................................................................................................................................................
Table 25-30 Configuring The Sim Linear Redundancy Check Block714................................................................................................................................................................
Configuring The Sim Cyclic Redundancy Check Block715................................................................................................................................................................
Using The Sim Receiver715................................................................................................................................................................
Table 25-31 Configuring The Sim Cyclic Redundancy Check Block715................................................................................................................................................................
Receive Parity Errors And Parity Nack Generation716................................................................................................................................................................
Receive Frame Errors716................................................................................................................................................................
Receive Overrun Errors And Overrun Nack Generation716................................................................................................................................................................
Using Initial Character Mode And Resulting Receive Data Formats717................................................................................................................................................................
Initial Character Mode Programming717................................................................................................................................................................
Automatic Receiver Mode718................................................................................................................................................................
Using The Sim Receiver With T = 1 Smartcards718................................................................................................................................................................
Using The Sim Transmitter718................................................................................................................................................................
Transmit Data Formats719................................................................................................................................................................
Transmit Nacks719................................................................................................................................................................
Transmit Guard Time720................................................................................................................................................................
Using The Sim Transmit With T = 1 Smartcards720................................................................................................................................................................
Answer To Reset (atr) Detection721................................................................................................................................................................
Suggested Programming Models For Specific Smartcards721................................................................................................................................................................
Programming Considerations722................................................................................................................................................................
Geldkate Cards723................................................................................................................................................................
T = 0 Smartcards723................................................................................................................................................................
Figure 25-16 Suggested T = 1, Emv, And Geldkate Compliant Sim Initialization723................................................................................................................................................................
T = 1 Smartcards724................................................................................................................................................................
Figure 26-1 General-purpose Timers Block Diagram727................................................................................................................................................................
Pin Configuration For General-purpose Timers728................................................................................................................................................................
Table 26-1 Pin Configuration728................................................................................................................................................................
Timer Control Registers 1 And 2729................................................................................................................................................................
Table 26-2 Gp Timers Module Register Memory Map729................................................................................................................................................................
Table 26-3 Timer 1 And 2 Control Registers Description730................................................................................................................................................................
Timer Prescaler Registers 1 And 2731................................................................................................................................................................
Table 26-4 Timer 1 And 2 Prescaler Registers Description731................................................................................................................................................................
Timer Compare Registers 1 And 2732................................................................................................................................................................
Table 26-5 Timer 1 And 2 Compare Registers Description732................................................................................................................................................................
Timer Capture Registers 1 And 2733................................................................................................................................................................
Table 26-6 Timer 1 And 2 Capture Registers Description733................................................................................................................................................................
Timer Counter Registers 1 And 2734................................................................................................................................................................
Table 26-7 Timer 1 And 2 Counter Registers Description734................................................................................................................................................................
Timer Status Registers 1 And 2735................................................................................................................................................................
Table 26-8 Timer 1 And 2 Status Registers Description735................................................................................................................................................................
Module Interface738................................................................................................................................................................
Table 27-1 Uart Module Interface Signals738................................................................................................................................................................
Pin Configuration For Uart1 And Uart2739................................................................................................................................................................
Table 27-2 Pin Configuration739................................................................................................................................................................
Interrupts And Dma Requests740................................................................................................................................................................
Table 27-3 Interrupts And Dma740................................................................................................................................................................
General Uart Definitions741................................................................................................................................................................
Rts—uart Request To Send742................................................................................................................................................................
Rts Edge Triggered Interrupt742................................................................................................................................................................
Figure 27-1 General Connections For A Uart With A Modem742................................................................................................................................................................
Table 27-4 Rts Edge Triggered Interrupt Truth Table742................................................................................................................................................................
Dtr—data Terminal Ready743................................................................................................................................................................
Dtr Edge Triggered Interrupt743................................................................................................................................................................
Table 27-5 Dtr Edge Triggered Interrupt Truth Table743................................................................................................................................................................
Dsr—data Set Ready744................................................................................................................................................................
Dcd—data Carrier Detect744................................................................................................................................................................
Ri—ring Indicator744................................................................................................................................................................
Cts—clear To Send744................................................................................................................................................................
Programmable Cts Deassertion744................................................................................................................................................................
Txd—uart Transmit744................................................................................................................................................................
Rxd—uart Receive744................................................................................................................................................................
Sub-block Description745................................................................................................................................................................
Figure 27-2 Uart Block Diagram And Clock Generation Diagram745................................................................................................................................................................
Transmitter746................................................................................................................................................................
Transmitter Fifo Empty Interrupt Suppression746................................................................................................................................................................
Receiver747................................................................................................................................................................
Idle Line Detect748................................................................................................................................................................
Idle Condition Detect Configuration748................................................................................................................................................................
Table 27-6 Idle Detection Truth Table748................................................................................................................................................................
Receiver Wake749................................................................................................................................................................
Receiving A Break Condition749................................................................................................................................................................
Vote Logic749................................................................................................................................................................
Binary Rate Multiplier (brm)750................................................................................................................................................................
Table 27-7 Majority Vote Results750................................................................................................................................................................
Baud Rate Automatic Detection Logic752................................................................................................................................................................
Figure 27-4 Baud Rate Detection Protocol Diagram752................................................................................................................................................................
Table 27-8 Baud Rate Automatic Detection752................................................................................................................................................................
Baud Rate Automatic Detection Protocol753................................................................................................................................................................
Table 27-9 Highest Baud Rates753................................................................................................................................................................
Escape Sequence Detection754................................................................................................................................................................
Table 27-10 Escape Timer Scaling754................................................................................................................................................................
Infrared Interface755................................................................................................................................................................
Table 27-11 Uart Module Register Memory Map755................................................................................................................................................................
Uart Receiver Registers758................................................................................................................................................................
And Uart2 Receiver Register N Description758................................................................................................................................................................
Uart Transmitter Registers760................................................................................................................................................................
And Uart2 Transmitter Register N Description760................................................................................................................................................................
Uart Control Register 1761................................................................................................................................................................
Table 27-14 Uart1 Control Register 1 And Uart2 Control Register 1 Description761................................................................................................................................................................
Uart Control Register 2764................................................................................................................................................................
Table 27-15 Uart1 Control Register 2 And Uart2 Control Register 2 Description764................................................................................................................................................................
Uart Control Register 3767................................................................................................................................................................
Uart1 Control Register 3767................................................................................................................................................................
Table 27-16 Uart1 Control Register 3 Description767................................................................................................................................................................
Uart2 Control Register 3769................................................................................................................................................................
Table 27-17 Uart1 Control Register 3 And Uart2 Control Register 3 Description769................................................................................................................................................................
Uart Control Register 4771................................................................................................................................................................
Table 27-18 Uart1 Control Register 4 And Uart2 Control Register 4 Description771................................................................................................................................................................
Uart Fifo Control Registers773................................................................................................................................................................
And Uart2 Fifo Control Register Description773................................................................................................................................................................
Uart Status Register 1775................................................................................................................................................................
Table 27-20 Uart1 Status Register 1 And Uart2 Status Register 1 Description775................................................................................................................................................................
Uart Status Register 2777................................................................................................................................................................
Table 27-21 Uart1 Status Register 2 And Uart2 Status Register 2 Description777................................................................................................................................................................
Uart Escape Character Registers779................................................................................................................................................................
Uart Escape Timer Registers780................................................................................................................................................................
And Uart2 Escape Timer Register Description780................................................................................................................................................................
Uart Brm Incremental Registers781................................................................................................................................................................
And Uart2 Brm Incremental Register Description781................................................................................................................................................................
Uart Brm Modulator Registers782................................................................................................................................................................
And Uart2 Brm Modulator Register Description782................................................................................................................................................................
Uart Baud Rate Count Registers783................................................................................................................................................................
And Uart2 Baud Rate Count Register Description783................................................................................................................................................................
Uart Brm Incremental Preset Registers 1–4784................................................................................................................................................................
Table 27-27 Uart Brm Incremental Preset Registers 1–4 Description784................................................................................................................................................................
Uart Brm Modulator Preset Registers 1-4785................................................................................................................................................................
Table 27-28 Uart Brm Modulator Preset Registers 1–4 Description785................................................................................................................................................................
Uart Test Register 1786................................................................................................................................................................
Table 27-29 Uart1 Test Register 1 And Uart2 Test Register 1 Description786................................................................................................................................................................
Uart Operation In Low-power System States787................................................................................................................................................................
Figure 27-5 Majority Vote Results788................................................................................................................................................................
Figure 27-6 Baud Rate Detection Of Divisor = 1788................................................................................................................................................................
Table 28-1 Endpoint Configurations790................................................................................................................................................................
Module Components791................................................................................................................................................................
Universal Serial Bus Device Controller791................................................................................................................................................................
Figure 28-1 Usb Device Module Block Diagram791................................................................................................................................................................
Synchronization And Transaction Decode792................................................................................................................................................................
Endpoint Fifo Architecture792................................................................................................................................................................
Control Logic793................................................................................................................................................................
Usb Transceiver Interface793................................................................................................................................................................
Figure 28-2 Usb Module Transceiver Interface793................................................................................................................................................................
Pin Configuration For Usb794................................................................................................................................................................
Table 28-2 Pin Configuration For Usb Module794................................................................................................................................................................
Table 28-3 Usb Module Register Memory Map795................................................................................................................................................................
Usb Frame Number And Match Register796................................................................................................................................................................
Table 28-4 Usb Frame Number And Match Register Description796................................................................................................................................................................
Usb Specification And Release Number Register797................................................................................................................................................................
Table 28-5 Usb Specification And Release Number Register Description797................................................................................................................................................................
Usb Status Register798................................................................................................................................................................
Table 28-6 Usb Status Register Description798................................................................................................................................................................
Usb Control Register799................................................................................................................................................................
Table 28-7 Usb Control Register Description799................................................................................................................................................................
Table 28-8 Device Request Status800................................................................................................................................................................
Usb Descriptor Ram Address Register801................................................................................................................................................................
Table 28-9 Usb Descriptor Ram Address Register Description801................................................................................................................................................................
Usb Descriptor Ram/endpoint Buffer Data Register802................................................................................................................................................................
Table 28-10 Usb Descriptor Ram/endpoint Buffer Data Register Description802................................................................................................................................................................
Usb Interrupt Status Register803................................................................................................................................................................
Table 28-11 Usb Interrupt Status Register Description803................................................................................................................................................................
Usb Interrupt Mask Register805................................................................................................................................................................
Table 28-12 Usb Interrupt Mask Register Description805................................................................................................................................................................
Usb Enable Register806................................................................................................................................................................
Table 28-13 Usb Enable Register Description806................................................................................................................................................................
Endpoint N Status/control Registers807................................................................................................................................................................
Table 28-14 Endpoint N Status/control Registers Description807................................................................................................................................................................
Endpoint N Interrupt Status Registers808................................................................................................................................................................
Table 28-15 Endpoint N Interrupt Status Registers Description809................................................................................................................................................................
Endpoint N Interrupt Mask Registers811................................................................................................................................................................
Table 28-16 Endpoint N Interrupt Mask Registers Description811................................................................................................................................................................
Endpoint N Fifo Data Registers813................................................................................................................................................................
Table 28-17 Endpoint N Fifo Data Registers Description813................................................................................................................................................................
Endpoint N Fifo Status Registers814................................................................................................................................................................
Table 28-18 Endpoint N Fifo Status Registers Description814................................................................................................................................................................
Endpoint N Fifo Control Registers816................................................................................................................................................................
Table 28-19 Endpoint N Fifo Control Registers Description816................................................................................................................................................................
Endpoint N Last Read Frame Pointer Registers818................................................................................................................................................................
Table 28-20 Endpoint N Last Read Frame Pointer Registers Description818................................................................................................................................................................
Endpoint N Last Write Frame Pointer Registers819................................................................................................................................................................
Table 28-21 Endpoint N Last Write Frame Pointer Registers Description819................................................................................................................................................................
Endpoint N Fifo Alarm Registers820................................................................................................................................................................
Table 28-22 Endpoint N Fifo Alarm Registers Description820................................................................................................................................................................
Endpoint N Fifo Read Pointer Registers821................................................................................................................................................................
Endpoint N Fifo Write Pointer Registers821................................................................................................................................................................
Table 28-23 Endpoint N Fifo Read Pointer Registers Description821................................................................................................................................................................
Device Initialization822................................................................................................................................................................
Table 28-24 Endpoint N Fifo Write Pointer Registers Description822................................................................................................................................................................
Configuration Download823................................................................................................................................................................
Table 28-25 Endptbuf—udc Endpoint Buffers Format824................................................................................................................................................................
Usb Endpoint To Fifo Mapping825................................................................................................................................................................
Endpoint Registers825................................................................................................................................................................
Enable The Device825................................................................................................................................................................
Exception Handling826................................................................................................................................................................
Unable To Complete Device Request826................................................................................................................................................................
Aborted Device Request826................................................................................................................................................................
Unable To Fill Or Empty Fifo Due To Temporary Problem826................................................................................................................................................................
Catastrophic Error827................................................................................................................................................................
Data Transfer Operations827................................................................................................................................................................
Usb Packets827................................................................................................................................................................
Short Packets827................................................................................................................................................................
Sending Packets827................................................................................................................................................................
Receiving Packets828................................................................................................................................................................
Programming The Fifo Controller828................................................................................................................................................................
Usb Transfers829................................................................................................................................................................
Data Transfers To The Host829................................................................................................................................................................
Data Transfers To The Device829................................................................................................................................................................
Control Transfers830................................................................................................................................................................
Bulk Traffic830................................................................................................................................................................
Bulk Out830................................................................................................................................................................
Bulk In830................................................................................................................................................................
Interrupt Traffic831................................................................................................................................................................
Isochronous Operations831................................................................................................................................................................
Isochronous Transfers In A Nutshell831................................................................................................................................................................
The Synch_frame Standard Request832................................................................................................................................................................
Interrupt Services832................................................................................................................................................................
Usb General Interrupts832................................................................................................................................................................
Msof—missed Start-of-frame832................................................................................................................................................................
Sof—start-of-frame832................................................................................................................................................................
Reset_stop—end Of Usb Reset Signaling832................................................................................................................................................................
Reset_start—start Of Usb Reset Signaling832................................................................................................................................................................
Wakeup—resume (wake-up) Signaling Detected833................................................................................................................................................................
Susp—usb Suspended833................................................................................................................................................................
Frame_match—match Detected In Usb_frame Register833................................................................................................................................................................
Cfg_chg—host Changed Usb Device Configuration833................................................................................................................................................................
Endpoint Interrupts833................................................................................................................................................................
Fifo_full833................................................................................................................................................................
Fifo_empty833................................................................................................................................................................
Fifo_error833................................................................................................................................................................
Fifo_high833................................................................................................................................................................
Fifo_low834................................................................................................................................................................
Eot—end Of Transfer834................................................................................................................................................................
Devreq—device Request834................................................................................................................................................................
Mdevreq—multiple Device Request834................................................................................................................................................................
Eof—end Of Frame834................................................................................................................................................................
Interrupts, Missed Interrupts And The Usb834................................................................................................................................................................
Cfg_chg835................................................................................................................................................................
Devreq835................................................................................................................................................................
Hard Reset835................................................................................................................................................................
Usb Software Reset835................................................................................................................................................................
Udc Reset835................................................................................................................................................................
Usb Reset Signaling836................................................................................................................................................................
Interface Features837................................................................................................................................................................
Clock Synchronization840................................................................................................................................................................
Figure 29-3 Repeated Start840................................................................................................................................................................
Figure 29-4 Synchronized Clock Scl840................................................................................................................................................................
Arbitration Procedure841................................................................................................................................................................
Handshaking841................................................................................................................................................................
Clock Stretching841................................................................................................................................................................
Table 29-1 Pin Configuration841................................................................................................................................................................
Table 29-4 Ifdr Register Description844................................................................................................................................................................
Table 29-5 Hclk Dividers845................................................................................................................................................................
Table 29-7 I2sr Register Description848................................................................................................................................................................
Table 29-8 I2dr Register Description850................................................................................................................................................................
Initialization Sequence851................................................................................................................................................................
Generation Of Start851................................................................................................................................................................
Post-transfer Software Response851................................................................................................................................................................
Generation Of Stop852................................................................................................................................................................
Generation Of Repeated Start852................................................................................................................................................................
Slave Mode852................................................................................................................................................................
Arbitration Lost852................................................................................................................................................................
Ssi Architecture855................................................................................................................................................................
Figure 30-1 Mc9328mx1 Input/output Block Diagram856................................................................................................................................................................
Figure 30-2 Ssi Block Diagram857................................................................................................................................................................
Ssi Clocking858................................................................................................................................................................
Normal Operating Mode858................................................................................................................................................................
Master / Synchronous Mode858................................................................................................................................................................
Ssi Clock And Frame Sync Generation858................................................................................................................................................................
Figure 30-3 Ssi Clocking858................................................................................................................................................................
Pin Configuration For Ssi859................................................................................................................................................................
Figure 30-4 Ssi Transmit Clock Generator Block Diagram859................................................................................................................................................................
Figure 30-5 Ssi Transmit Frame Sync Generator Block Diagram859................................................................................................................................................................
Table 30-1 Pin Configuration860................................................................................................................................................................
Pin Configuration Example Software861................................................................................................................................................................
Table 30-2 Ssi Module Register Memory Map861................................................................................................................................................................
Ssi Transmit Data Register862................................................................................................................................................................
Ssi Transmit Fifo Register863................................................................................................................................................................
Ssi Transmit Shift Register863................................................................................................................................................................
Table 30-3 Ssi Transmit Data Register Description863................................................................................................................................................................
Figure 30-6 Transmit Data Path (txbit0 = 0, Tshfd = 0)864................................................................................................................................................................
Table 30-4 Data Bit Shifting Configuration864................................................................................................................................................................
Figure 30-7 Transmit Data Path (txbit0 = 0, Tshfd = 1)865................................................................................................................................................................
Figure 30-8 Transmit Data Path (txbit0 = 1, Tshfd = 0)865................................................................................................................................................................
Figure 30-9 Transmit Data Path (txbit0 = 1, Tshfd = 1)865................................................................................................................................................................
Ssi Receive Data Register866................................................................................................................................................................
Ssi Receive Fifo Register866................................................................................................................................................................
Table 30-5 Ssi Receive Data Register Description866................................................................................................................................................................
Ssi Receive Shift Register867................................................................................................................................................................
Table 30-6 Data Bit Shifting Configuration867................................................................................................................................................................
Figure 30-10 Receive Data Path (rxbit0 = 0, Rshfd = 0)868................................................................................................................................................................
Figure 30-11 Receive Data Path (rxbit0 = 0, Rshfd = 1)868................................................................................................................................................................
Figure 30-12 Receive Data Path (rxbit0 = 1, Rshfd = 0)868................................................................................................................................................................
Ssi Control/status Register869................................................................................................................................................................
Figure 30-13 Receive Data Path (rxbit0 = 1, Rshfd = 1)869................................................................................................................................................................
Table 30-7 Ssi Control/status Register Description869................................................................................................................................................................
I2s Mode Selection873................................................................................................................................................................
Ssi Transmit Configuration Register874................................................................................................................................................................
Table 30-10 Ssi Transmit Configuration Register Description875................................................................................................................................................................
Ssi Receive Configuration Register877................................................................................................................................................................
Table 30-11 Ssi Transmit Data Interrupts877................................................................................................................................................................
Table 30-12 Ssi Receive Configuration Register Description878................................................................................................................................................................
Table 30-13 Ssi Receive Data Interrupts880................................................................................................................................................................
Table 30-14 Clock Pin Configuration880................................................................................................................................................................
Ssi Transmit Clock Control Register And Ssi Receive Clock Control Register881................................................................................................................................................................
Calculating The Ssi Bit Clock From The Input Clock Value882................................................................................................................................................................
Table 30-16 Ssi Bit And Frame Clock As A Function Of Psr And Pm In Normal Mode883................................................................................................................................................................
Table 30-17 Ssi Sys, Bit And Frame Clock In Master Mode883................................................................................................................................................................
Ssi Time Slot Register884................................................................................................................................................................
Table 30-18 Ssi Time Slot Register Description884................................................................................................................................................................
Ssi Fifo Control/status Register885................................................................................................................................................................
Table 30-19 Ssi Fifo Control/status Register Description885................................................................................................................................................................
Table 30-20 Value Of Transmit Fifo Empty (tfe) And Receive Fifo Full (rff)887................................................................................................................................................................
Ssi Option Register888................................................................................................................................................................
Table 30-21 Ssi Option Register Description888................................................................................................................................................................
Ssi Data And Control Pins889................................................................................................................................................................
Ssi_txdat, Serial Transmit Data889................................................................................................................................................................
Ssi_rxdat, Serial Receive Data889................................................................................................................................................................
Ssi_txclk, Serial Transmit Clock889................................................................................................................................................................
Ssi_rxclk, Serial Receive Clock889................................................................................................................................................................
Table 30-22 Ssi Pin Description889................................................................................................................................................................
Ssi_txfs, Serial Transmit Frame Sync890................................................................................................................................................................
Ssi_rxfs, Serial Receive Frame Sync890................................................................................................................................................................
Figure 30-14 Asynchronous (syn = 0) Ssi Configurations—continuous Clock890................................................................................................................................................................
Figure 30-15 Synchronous Ssi Configurations—continuous And Gated Clock891................................................................................................................................................................
Figure 30-16 Serial Clock And Frame Sync Timing891................................................................................................................................................................
Ssi Operating Modes892................................................................................................................................................................
Table 30-23 Ssi Operating Modes892................................................................................................................................................................
Normal Mode893................................................................................................................................................................
Normal Mode Transmit893................................................................................................................................................................
Normal Mode Receive893................................................................................................................................................................
Figure 30-17 Normal Mode Timing—continuous Clock894................................................................................................................................................................
Figure 30-18 Normal Mode Timing—gated Clock894................................................................................................................................................................
Network Mode895................................................................................................................................................................
Network Mode Transmit895................................................................................................................................................................
Network Mode Receive896................................................................................................................................................................
Gated Clock Mode897................................................................................................................................................................
Figure 30-19 Network Mode Timing—continuous Clock897................................................................................................................................................................
External Frame And Clock Operation898................................................................................................................................................................
Ssi Reset And Initialization Procedure898................................................................................................................................................................
Figure 30-20 Rising Edge Clocking With Falling Edge Latching898................................................................................................................................................................
Figure 30-21 Falling Edge Clocking With Rising Edge Latching898................................................................................................................................................................
Table 30-24 Ssi Control Bits Requiring Reset Before Change899................................................................................................................................................................
Csi Module Architecture901................................................................................................................................................................
Csi Module Interface Signal Description902................................................................................................................................................................
Figure 31-1 Csi Module Block Diagram902................................................................................................................................................................
Table 31-1 Csi Module Interface Signal Description902................................................................................................................................................................
Pin Configuration For Csi903................................................................................................................................................................
Csi Module Operation903................................................................................................................................................................
Table 31-2 Cmos Interface Signals903................................................................................................................................................................
Table 31-3 Pin Configuration903................................................................................................................................................................
Csi Interrupt Operation904................................................................................................................................................................
Register Access When Csi Module Is Disabled904................................................................................................................................................................
Table 31-4 Csi Module Register Memory Map904................................................................................................................................................................
Csi Control Register 1905................................................................................................................................................................
Table 31-5 Csi Control Register 1 Description905................................................................................................................................................................
Csi Control Register 2908................................................................................................................................................................
Table 31-6 Csi Control Register 2 Description908................................................................................................................................................................
Csi Status Register 1910................................................................................................................................................................
Table 31-7 Csi Status Register 1 Description910................................................................................................................................................................
Csi Statistic Fifo Register 1911................................................................................................................................................................
Table 31-8 Csi Statistic Fifo Register 1 Description911................................................................................................................................................................
Csi Rxfifo Register 1912................................................................................................................................................................
Table 31-9 Csi Module Fifo Register Storage Scheme912................................................................................................................................................................
Table 31-10 Csi Rxfifo Register 1 Description912................................................................................................................................................................
Statistic Data Generation913................................................................................................................................................................
Statistic Block Diagram And Description913................................................................................................................................................................
Auto Exposure And Auto White Balance913................................................................................................................................................................
Figure 31-2 Statistic Block Diagram913................................................................................................................................................................
Figure 31-3 Statistic Blocks Example For 288 X 216 Pixels Image Size914................................................................................................................................................................
Table 31-11 Block Size For Live View Lcd Size914................................................................................................................................................................
Auto Focus915................................................................................................................................................................
Packing Of Statistic Data915................................................................................................................................................................
Figure 31-4 Full Resolution Statistic Example915................................................................................................................................................................
Sensor Interface Signals916................................................................................................................................................................
Statistic Control Signals916................................................................................................................................................................
Start Of Frame916................................................................................................................................................................
Auto Focus Spread916................................................................................................................................................................
Statistic Output And Dma Signals916................................................................................................................................................................
Statistic Data Out916................................................................................................................................................................
Statistic Fifo Full916................................................................................................................................................................
Statistic Data Request916................................................................................................................................................................
Figure 31-5 Auto Focus Spread916................................................................................................................................................................
General Description917................................................................................................................................................................
Gpio Module Overview918................................................................................................................................................................
Gpio Module Features918................................................................................................................................................................
Figure 32-1 Top Level Of Circuitry For Port X, Pin [i]918................................................................................................................................................................
Interrupts919................................................................................................................................................................
Gpio Signal Description919................................................................................................................................................................
Table 32-1 Gpio External Pins Description919................................................................................................................................................................
Gpio Module Block Diagram920................................................................................................................................................................
Pin Configuration For Gpio920................................................................................................................................................................
Figure 32-2 Gpio Module Block Diagram For Port X, Pin [i]920................................................................................................................................................................
Table 32-2 Pin Configuration921................................................................................................................................................................
Table 32-3 Gpio Multiplexing Table With Ain, Bin, Cin, Aout, And Bout922................................................................................................................................................................
Table 32-4 Gpio Module Register Memory Map924................................................................................................................................................................
Data Direction Registers925................................................................................................................................................................
Table 32-5 Data Direction Registers Description925................................................................................................................................................................
Output Configuration Registers926................................................................................................................................................................
Output Configuration Register 1926................................................................................................................................................................
Table 32-6 Output Configuration Register 1 Description926................................................................................................................................................................
Output Configuration Register 2927................................................................................................................................................................
Table 32-7 Output Configuration Register 2 Description927................................................................................................................................................................
Input Configuration Registers928................................................................................................................................................................
Input Configuration Register A1928................................................................................................................................................................
Table 32-8 Input Configuration Register A1 Description928................................................................................................................................................................
Input Configuration Register A2929................................................................................................................................................................
Table 32-9 Input Configuration Register A2 Description929................................................................................................................................................................
Input Configuration Register B1930................................................................................................................................................................
Table 32-10 Input Configuration Register B1 Description930................................................................................................................................................................
Input Configuration Register B2931................................................................................................................................................................
Table 32-11 Input Configuration Register B2 Description931................................................................................................................................................................
Data Registers932................................................................................................................................................................
Table 32-12 Data Register Description932................................................................................................................................................................
Gpio In Use Registers933................................................................................................................................................................
Table 32-13 Gpio In Use Register Description933................................................................................................................................................................
Sample Status Registers934................................................................................................................................................................
Table 32-14 Sample Status Register Description934................................................................................................................................................................
Interrupt Configuration Registers935................................................................................................................................................................
Interrupt Configuration Register 1935................................................................................................................................................................
Table 32-15 Interrupt Configuration Register 1 Description935................................................................................................................................................................
Interrupt Configuration Register 2936................................................................................................................................................................
Table 32-16 Interrupt Configuration Register 2 Description936................................................................................................................................................................
Interrupt Mask Registers937................................................................................................................................................................
Table 32-17 Interrupt Mask Register Description937................................................................................................................................................................
Interrupt Status Registers938................................................................................................................................................................
Table 32-18 Interrupt Status Register Description938................................................................................................................................................................
General Purpose Registers939................................................................................................................................................................
Table 32-19 General Purpose Register Description939................................................................................................................................................................
Software Reset Registers940................................................................................................................................................................
Table 32-20 Software Reset Register Description940................................................................................................................................................................
Pull_up Enable Registers941................................................................................................................................................................
Table 32-21 Pull_up Enable Register Description941................................................................................................................................................................
I 2 C Frequency Divider Register950................................................................................................................................................................

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