Motorola PowerQUICC II MPC8280 Series Reference Manual page 408

Message Unit (I O)
2
Table 9-61 describes OMIMR fields.
Bits Name
31–6 —
5 OPQIM
4 —
3 ODIM
2 —
1 OM1IM
0 OM0IM
9.12.3.4.5 Inbound Message Interrupt Status Register (IMISR)
This register contains the interrupt status of the I
Writing a 1 to the corresponding set bit will clear the bit. The events are generated by the
PCI masters. IMISR should be accessed only from the 60x bus and only in agent mode.
Accesses while in host mode or from the PCI bus have undefined results.
31
Field
Reset
R/W
Addr
15
Field
Reset
R/W
Addr
Figure 9-77. Inbound Message Interrupt Status Register (IMISR)
9-86
Freescale Semiconductor, Inc.
Table 9-61. OMIMR Field Descriptions
R/W
R Reserved, should be cleared.
RW Outbound post queue interrupt mask
0 Outbound post queue interrupt is allowed.
1 Outbound post queue interrupt is masked.
R Reserved, should be cleared.
RW Outbound doorbell interrupt mask
0 Outbound doorbell interrupt is allowed.
1 Outbound doorbell interrupt is masked.
R Reserved, should be cleared.
RW Outbound message 1 interrupt mask
0 Outbound message 1 interrupt is allowed.
1 Outbound message 1 interrupt is masked.
RW Outbound message 0 interrupt mask
0 Outbound message 0 interrupt is allowed.
1 Outbound message 0 interrupt is masked.
0000_0000_0000_0000
Refer to Table 9-62.
9
—
0000_0000_0000_0000
Refer to Table 9-62.
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Description
O, door bell, and message register events.
2
—
0x10482
8 7 6 5
OFOI IPOI — IPQI MCI
0x10480
16
4 3 2 1 0
IDI — IM1I IM0I
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