Motorola PowerQUICC II MPC8280 Series Reference Manual page 421

9.13.1.6.5 DMA Destination Address Registers 0–3 (DMADARx)
The destination address register, shown in Figure 9-86, indicates the address where the
DMA controller will be writing data to. This address can be in either PCI memory or 60x
memory. The software has to ensure that this is a valid memory address.
The choice between PCI or 60x is done according to the following rule: If the address hits
one of the PCI outbound windows, then the destination data is written to the PCI memory.
Otherwise, it is written to the 60x memory. Refer to Figure 9-13.
31
Field
Reset
R/W
Addr 0x1051A (DMAADAR0); 0x1059A (DMAADAR1); 0x1061A (DMAADAR2); 0x1069A (DMAADAR3)
15
Field
Reset
R/W
Addr 0x10518 (DMAADAR0); 0x10598 (DMAADAR1); 0x10618 (DMAADAR2); 0x10698 (DMAADAR3)
Figure 9-86. DMA Destination Address Registers 0–3 (DMADARx)
Table 9-70 describes DMADARx fields.
Bit Name
31–0 DA
9.13.1.6.6 DMA Byte Count Registers 0–3 (DMABCRx)
This register contains the number of bytes per transfer (maximum transfer size is
64 Mbytes).
MOTOROLA
Freescale Semiconductor, Inc.
0000_0000_0000_0000
0000_0000_0000_0000
Table 9-70. DMADARx Field Descriptions
Destination address. The content is updated after every DMA write operation.
Chapter 9. PCI Bridge
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DA
R/W
DA
R/W
Description
DMA Controller
16
0
9-99