Reset 0000_0000_0000_0000; R/W R/W; Addr; Bits Name Description - Motorola PowerQUICC II MPC8280 Series Reference Manual

DMA Controller
31

Field

Reset
R/W

Addr

15
Field
Reset
R/W
Addr
Figure 9-80. Queue Base Address Register (QBAR)
Table 9-65 describes QBAR fields.
Bits Name Access
31–20 QBA RW
19–0 — R
9.13 DMA Controller
The PCI bridge's DMA controller transfers blocks of data independent of the local core or
PCI hosts. Data movement occurs on the PCI and/or 60x bus. The PCI Bridge's DMA
module has four high-speed DMA channels with an aggregate bandwidth conservatively
estimated at 210 Mbytes per second, for 60x to PCI transfer. The channels share 144 bytes
of DMA-dedicated buffer space to facilitate the gathering and sending of data. Both the
local core and PCI masters can initiate a DMA transfer.
Features of the DMA controller include the following:
• 4 channels
• Concurrent execution across multiple channels with programmable bandwidth
control
• All channels are accessible by local core and remote PCI masters.
• Unaligned transfer capability
• Data chaining and direct mode
• Interrupt on completed segment, chain, and error
• Supports all transfer combinations between 60x memory and PCI memory:
60x-to-60x, PCI-to-PCI, 60x-to-PCI, and PCI-to-60x.
9-90
Freescale Semiconductor, Inc.
QBA
0000_0000_0000_0000
0000_0000_0000_0000
Table 9-65. QBAR Field Descriptions
Queue base address. Base address of circular queue in local memory. It must be
aligned to a 1Mbyte boundary.
Reserved, should be cleared.
MPC8280 PowerQUICC II Family Reference Manual
For More Information On This Product,
Go to: www.freescale.com
20
R/W
0x104F2
—
R/W
0x104F0
Description
19 16
—
0
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