Motorola PowerQUICC II MPC8280 Series Reference Manual page 401

31
Field
Reset
R/W
Addr
15
Field
Reset
R/W
Addr
Figure 9-68. Inbound Post_FIFO Tail Pointer Register (IPTPR)
Bits Name
31–20 QBA Queue base address. When read returns the contents of QBAR bits 31-20.
19–2 IPTP Inbound post_FIFO tail pointer. Local memory offset of the tail pointer of the inbound post list
FIFO.
1–0 — Reserved, should be cleared.
9.12.3.3 Outbound FIFOs
The outbound queues are used to send messages from the local processor to a remote host
processor. I O defines two outbound FIFOs—an outbound post FIFO and an outbound free
2
FIFO.
The following registers should be accessed only from the 60x bus and only in agent mode.
Accesses while in host mode or from the PCI bus have undefined results.
9.12.3.3.1 Outbound Free_FIFO Head Pointer Register (OFHPR) and
Outbound Free_FIFO Tail Pointer Register (OFTPR)
The outbound free list FIFO holds the MFAs of the empty outbound message locations in
local memory. When the local processor is ready to send an outbound message, it first
fetches an empty MFA by reading the OFTPR. It then writes the message into the MFA.
The OFTPR is managed by the local processor.
When an external PCI master has completed use of a message that was posted in the
outbound post FIFO and wants to return the MFA to the free list, it writes to OFQPR (refer
to Section 9.12.3.4.2, "Outbound FIFO Queue Port Register (OFQPR)"). The PCI bridge's
I O unit then writes the MFA to the OFHPR. This, in turn, causes the outbound free head
2
pointer to be advanced.
MOTOROLA
Freescale Semiconductor, Inc.
QBA
0000_0000_0000_0000
R
IPTP
0000_0000_0000_0000
R/W
Table 9-53. IPTPR Field Descriptions
Chapter 9. PCI Bridge
For More Information On This Product,
Go to: www.freescale.com
20
0x104BA
0x104B8
Description
Message Unit (I O)
2
19 16
IPTP
R/W
2 1 0
—
R
9-79