Motorola PowerQUICC II MPC8280 Series Reference Manual page 431

Chapter 10
Clocks and Power Control
The MPC8280's clocking architecture includes two PLLs—the main PLL and the core
PLL. The main PLL, together with the dividers, provides the internal 60x bus clock and
internal clocks for all blocks in the chip except core blocks. The core PLL provides the
internal core clocks.
The MPC8280's clocking is a configurable system supporting three clock configuration
modes. The clock configuration mode is set during the power on reset.
CLKIN is the primary timing reference for the MPC8280. The frequency of CLKIN equals
60x and local bus frequencies. The main PLL multiplies the frequency of the input clock to
the final CPM frequency. Refer to Section 10.6, "Clock Configuration Modes."
10.1 MPC8280 Clock Block Diagram
The MPC8280 clocking system, shown in Figure 10-1, is designed around two PLLs—the
main PLL and the core PLL. The main PLL receives CLKIN as its input clock and
multiplies it to provide MAIN_CLK, which is twice the CPM clock, to the clock block
dividers. The dividers shown in Figure 10-1 generate all MPC8280 internal clocks by
synchronously dividing MAIN_CLK. These clocks are then output from the clock block to
the entire MPC8280.
10.1.1 Main PLL
The main PLL performs frequency multiplication and skew elimination. It allows the CPM
to operate at a high internal clock frequency while using a low-frequency clock input. This
has two immediate benefits:
• A lower clock input frequency reduces overall electromagnetic interference
generated by the system
• Oscillating at different frequencies eliminates the need for another oscillator
MOTOROLA
Freescale Semiconductor, Inc.
Chapter 10. Clocks and Power Control
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