Motorola PowerQUICC II MPC8280 Series Reference Manual page 419

Table 9-67 describes DMASRx fields.
Bits Name Access
31–8 — RW
7 TE Read/
Write 1 to
clear
6–3 — R
2 CB Read
Only
1 EOSI Read/
Write 1 to
clear
0 EOCDI Read/
Write 1 to
clear
9.13.1.6.3 DMA Current Descriptor Address Registers 0–3 (DMACDARx)
The current descriptor address register contains the address of the current segment
descriptor being transferred. In chaining mode, software must initialize this register to point
to the first descriptor in the chain. After processing the first descriptor, the DMA controller
moves the contents of the next descriptor address register into DMACDAR, loads the next
descriptor into DMANDAR, and executes the current transfer. This process continues until
encountering a descriptor whose EOTD (end-of-transfer descriptor) bit is set, which will be
the last descriptor to be executed.
31
Field
Reset
R/W
Addr 0x1050A(DMACDR0); 0x1058A (DMACDR1); 0x1060A (DMACDR2); 0x1068A (DMACDR3)
15
Field
Reset
R/W
Addr 0x10508 (DMACDR0); 0x10588 (DMACDR1); 0x10608 (DMACDR2); 0x10688 (DMACDR3)
Figure 9-84. DMA Current Descriptor Address Registers 0–3 (DMACDARx)
MOTOROLA
Freescale Semiconductor, Inc.
Table 9-67. DMASRx Field Descriptions
Reserved, should be cleared.
Transfer error. This bit is set when there is an error condition during the DMA transfer
and the TEM bit is cleared.
Reserved, should be cleared.
Channel busy. When set indicates that a DMA transfer is currently in progress. This
bit will be cleared as a result of any of the three following conditions: (1) an error, (2)
a halt, or (3) completion of the DMA transfer.
End-of-segment interrupt. After transferring a segment of data, if the EOSIE bit in the
current descriptor address register is set, then this bit will be set and an interrupt is
generated. Otherwise, no interrupt is generated.
End-of-chain/direct Interrupt. When the last DMA transfer is finished, either in
chaining or direct mode, if DMAMR[EOTIE] is set, this bit will be set and an interrupt
is generated. Otherwise, no interrupt is generated.
0000_0000_0000_0000
CDA
0000_0000_0000_0000
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Description
CDA
R/W
5 4
SNEN EOSIE
R/W
DMA Controller
16
3 2 0
—
9-97