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22.3.56 ADC Magnitude Compare Interrupt Enable Set Register (ADMAGINTENASET)
ADC Magnitude Compare Interrupt Enable Set Register (ADMAGINTENASET) is shown in
and described in
Table
Figure 22-87. ADC Magnitude Compare Interrupt Enable Set Register (ADMAGINTENASET)
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22-62. ADC Magnitude Compare Interrupt Enable Set Register (ADMAGINTENASET)
Bit
Field
31-3
Reserved
2-0
MAG_INT_ENA_SET
22.3.57 ADC Magnitude Compare Interrupt Enable Clear Register (ADMAGINTENACLR)
ADC Magnitude Compare Interrupt Enable Clear Register (ADMAGINTENACLR) is shown in
and described in
Table
Figure 22-88. ADC Magnitude Compare Interrupt Enable Clear Register (ADMAGINTENACLR)
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22-63. ADC Magnitude Compare Interrupt Enable Clear Register (ADMAGINTENACLR)
Bit
Field
31-3
Reserved
2-0
MAG_INT_ENA_CLR
SPNU563A – March 2018
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22-62.
[offset = 158h]
Reserved
R-0
Field Descriptions
Value
Description
0
Reads return 0. Writes have no effect.
Each of these three bits, when set, enable the corresponding magnitude compare interrupt.
Any operation mode read/write for each bit:
0
The enable status of the corresponding magnitude compare interrupt is left unchanged.
1
The corresponding magnitude compare interrupt is enabled.
22-63.
[offset = 15Ch]
Reserved
R-0
Field Descriptions
Value
Description
0
Reads return 0. Writes have no effect.
Each of these three bits, when set, enable the corresponding magnitude compare interrupt.
Any operation mode read/write for each bit:
0
The enable status of the corresponding magnitude compare interrupt is left unchanged.
1
The corresponding magnitude compare interrupt is disabled.
Copyright © 2018, Texas Instruments Incorporated
3
2
MAG_INT_ENA_SET
3
2
MAG_INT_ENA_CLR
Analog To Digital Converter (ADC) Module
ADC Registers
Figure 22-87
0
R/W-0
Figure 22-88
0
R/W-0
941
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