Renesas HD49335HNP Specification Sheet
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Renesas HD49335HNP Specification Sheet

Renesas HD49335HNP Specification Sheet

Cds/pga & 10-bit a/d tg converter
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HD49335NP/HNP
CDS/PGA & 10-bit A/D TG Converter
Description
The HD49335NP/HNP is a CMOS IC that provides CDS-PGA analog processing (CDS/PGA) suitable for CCD camera
digital signal processing systems together with a 10-bit A/D converter and timing generator in a single chip.
There are address map and timing generator charts besides this specification. May be contacted to our sales department
if examining the details.
Functions
• Correlated double sampling
• PGA
• Serial interface control
• 10-bit ADC
• Timing generator
• Operates using only the 3 V voltage
• Corresponds to switching mode of power dissipation and operating frequency
Power dissipation: 220 mW (Typ), maximum frequency: 36 MHz (HD49335HNP)
Power dissipation: 150 mW (Typ), maximum frequency: 25 MHz (HD49335NP)
• ADC direct input mode
• QFN 64-pin package
Features
• Suppresses low-frequency noise, which output from CCD by the correlated double sampling.
• The S/H response frequency characteristics for the reference level can be adjusted using values of external parts and
registers.
• High sensitivity is achieved due to the high S/N ratio and a wide dynamic range provided by a PG amplifier.
• PGA, pulse timing, standby mode, etc., is achieved via a serial interface.
• High precision is provided by a 10-bit-resolution A/D converter.
• Difference encoded gray code can be selected as an A/D output code. It is effective in suppression of solarization
(wave pattern). It is patented by Renesas.
• Timing generator generates the all of pulse which are needed for CCD driving.
Rev.1.0, Feb.12.2004, page 1 of 29
REJ03F0097-0100Z
Rev.1.0
Feb.12.2004

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  • Page 1 • Operates using only the 3 V voltage • Corresponds to switching mode of power dissipation and operating frequency Power dissipation: 220 mW (Typ), maximum frequency: 36 MHz (HD49335HNP) Power dissipation: 150 mW (Typ), maximum frequency: 25 MHz (HD49335NP) • ADC direct input mode •...

  • Page 2: Pin Arrangement

    CDS Digital ground + ADC output buffer ground (0 V) 3 to 12 D0 to D9 Digital output (D0; LSB, D9; MSB) ADC output buffer power supply (3 V) General ground for TG (0 V) CLK_in CLK input (max 72 MHz)
  • Page 3 L: Slave mode, H: Master mode DLL_C Analog delay DLL external C pin (100 pF for GND) Digital power supply (3 V) CDS, PAG, ADC part Pulse monitor (SP1, SP2, ADCK, OBP, CPDM, PBLK input) 41cont Input STROB = pin 41, Input SUB_SW = pin 39 at Low...
  • Page 4 HD49335NP/HNP Input/Output Equivalent Circuit Pin Name Digital output D0 to D9, HD_in, VD_in, H1A, H2A, 1/2clk_o, 1/4clk_o, 41cont, SUB_SW, SUB_PD ID, RG, MON, XV1 to XV4, CH1 to CH4, XSUB Digital input CLK_in, HD_in, VD_in, ADCLK, OBP, SPBLK, SPSIG, CS, SCK, SDATA, PBLK, OEB, Reset, Test1, Test2, SUB_SW, STROB Analog...

  • Page 5: Block Diagram

    HD49335NP/HNP Block Diagram SUB_SW SUB_PD STROB ADC_in CDS_in BLKSH BLKC DC offset compensation BLKFB circuit Rev.1.0, Feb.12.2004, page 5 of 29 Timing generator 10bit Serial Bias interface generator 1 to 4 Reset...

  • Page 6: Internal Functions

    HD49335NP/HNP Internal Functions Functional Description • CDS input  CCD low-frequency noise is suppressed by CDS (correlated double sampling).  The signal level is clamped at 14 LSB to 76 LSB by resister during the OB period. *  Gain can be adjusted using 8 bits of register (0.132 dB steps) within the range from –2.36 dB to 31.40 dB. * •...
  • Page 7 HD49335NP/HNP 3. Automatic Offset Calibration Function and Black-Level Clamp Data Settings The DAC DC voltage added to the output of the PGA amplifier is adjusted by automatic offset calibration. The data, which cancels the output offset of the PGA amplifier and the input offset of the ADC, and the clamp data (14 LSB to 76 LSB) set by register are added and input to the DAC.
  • Page 8 HD49335NP/HNP 6. ADC Digital Output Control Function The ADC digital output includes the functions output enable, code conversion, and test mode. Tables 3, 4 and 5 show the output functions and the codes. Table 3 ADC Digital Output Functions Hi-Z Same as in table 4.
  • Page 9 HD49335NP/HNP 7. Adjustment of Black-Level S/H Response Frequency Characteristics The CR time constant that is used for sampling/hold (S/H) at the black level can be adjusted by changing the register settings, as shown in table 6. Table 6 SHSW CR Time Constant Setting CR Time Constant (Typ) 2.20 nsec (cutoff frequency conversion)

  • Page 10: Timing Chart

    HD49335NP/HNP Timing Chart Figure 2 shows the timing chart when CDSIN and ADCIN input modes are used. When CDS_in input mode is used CDS_in ADCLK D0 to D9 N 10 When ADC_in input mode is used ADC_in ADCLK D0 to D9 Figure 2 Output Timing Chart when CDSIN and ADCIN Input Modes are Used •...
  • Page 11 HD49335NP/HNP Detailed Timing Specifications Detailed Timing Specifications when CDSIN Input Mode is Used Figure 3 shows the detailed timing specifications when the CDSIN input mode is used, and table 8 shows each timing specification. CDS_in ADCLK D0 to D9 Figure 3 Detailed Timing Chart when CDSIN Input Mode is Used Table 8 Timing Specifications when the CDSIN Input Mode is Used Timing...
  • Page 12 HD49335NP/HNP Detailed Timing Specifications at Pre-Blanking Figure 5 shows the pre-blanking detailed timing specifications. PBLK Digital output (D0 to D9) data Figure 5 Detailed Timing Specifications at Pre-Blanking Detailed Timing Specifications when ADCIN Input Mode is Used Figure 6 shows the detailed timing chart when ADCIN input mode is used, and table 9 shows each timing specification. ADC_in ADCLK D0 to D9...
  • Page 13 HD49335NP/HNP Dummy Clamp It adjusts the mis-clamp which occurs when taking the photo under the highlight conditions. (Like a sun) Normally it woks with the OB clamp, however when black level is out of the range caused by hightlight enter to OB part, it changes to clamp processing by dummy bit level.

  • Page 14: Absolute Maximum Ratings

    = 3.0 V, DV = 3.0 V, and R = 33 kΩ) BIAS Unit Test Conditions Remarks LoPwr = low * HD49335HNP LoPwr = high * HD49335NP CS, SCK, SDATA = –1 mA = +1 mA µA = 3.0 V µA...
  • Page 15 HD49335NP/HNP Electrical Characteristics (cont.) (Unless othewide specified, Ta = 25°C, AV • Items for CDSIN Input Mode Item Symbol Consumption current (1) Consumption current (2) CCD offset tolerance range Timing specifications (1) CDS1 Timing specifications (2) CDS2 Timing specifications (3) CDS3 Timing specifications (4) CDS4...
  • Page 16 HD49335NP/HNP Electrical Characteristics (cont.) (Unless othewide specified, Ta = 25°C, AV • Items for ADCIN Input Mode Item Symbol Consumption current (3) Consumption current (4) Timing specifications (14) ADC1 Timing specifications (15) ADC2 Timing specifications (16) ADC3 Timing specifications (17) AHLD4 Timing specifications (18) AOD5...
  • Page 17 HD49335NP/HNP Serial Interface Specifications Timing Specifications INT1 Latches SDATA at SCK rising edge SDATA STD2(Upper data) Figure 8 Serial Interface Timing Specifications Item — 5 MHz 50 ns — INT1,2 50 ns — 50 ns — The Kind of Data Data address has 256 type.
  • Page 18 HD49335NP/HNP Explanation of Serial Data of CDS Part Serial data of CDS part are assigned to address H’F0 to H’F8. Functions are follows. Address • PGA gain (D0 to D7 of address H’F0) Details are referred to page 5 block diagram. At CDS_in mode: –2.36 dB + 0.132 dB ×...
  • Page 19 HD49335NP/HNP • Output mode (D2 to D4 of address H’F1 and address H’F4 of D6) It is a test mode. Combination details are table 3 to 5. Normally set to all 0. • SHA-fsel (D8 to D9 of address H’F1) It is a LPF switching of SH amplifier.
  • Page 20 HD49335NP/HNP Address • MON (D0 to D2 of address H’F4) Select the pulse which output to pin MON (pin 60). When D0 to D2: 0, Fix to Low When 2, SP1 When 4, OBP When 6, CPDM • H12Baff (D3 to D6 of address H’F4) Select the buffer size which output to pin H1A, H2A (pin 22, 26).
  • Page 21 HD49335NP/HNP Ripple (pseudo outline made by quantized error) occurres on the point which swithing the ADC output multiple bit in parallel. When switching the several of ADC output at the same time, ripple (pseudo outline caused by miss quantization) occurs to the image. Differential code and gray code are recommended for this countermeasure.
  • Page 22 HD49335NP/HNP • Address H’F5 sets the DLL delay time and selects the 1/4 phase. Details are on the next page. And D15 of address H’F8 can switch 2/3 divided mode but ensure that this address data relative to valid/invalid. Divided mode D0 to D7 of address H’F5 D0 to D14 of address H’F8 •...
  • Page 23 HD49335NP/HNP (3) Setting method of DLL DLL step decides the how many divide the 1 cycle of sensor CLK. For reference, set 1 ns(when 2 ns DLL_current bit = 0, when 1 set to 1 ns) Can be set 16 to 64 steps by 4 steps. Steps = 4 + (4 N);...

  • Page 24: Operation Sequence At Power On

    H'00 to H'EF of TG part and H'F4 to H7F7 of CDS part should transfer in advance. Rev.1.0, Feb.12.2004, page 24 of 29 Must be stable within the operating power supply voltage range 3clk or more Note: At 2 divided mode: ADCLK = 1/2CLK_in...
  • Page 25 — — — — — — — — — — Power supply specification of H1, H2, RG are 3.0 V to 3.3 V. Values are sensor CLK = when 18 MHz. Unit — H1DL Load Unit capacitance — 165 pF —...

  • Page 26: Notice For Use

    3. As this IC is sensitive to power line noise, the ground impedance should be kept as small as possible. Also, to prevent latchup, a ceramic capacitor of 0.1 µF or more and an electrolytic capacitor of 10 µF or more should be inserted between the ground and power supply. 4. Common connection of AV and DV the phase difference should be 0.3 V or less at power-on and 0.1 V or less during operation.
  • Page 27 HD49335NP/HNP Example of Recommended External Circuit Slave mode Pin 57(Test1 = Low) 3.0V 47/6 to V.Baff XSUB SUB_SW/ADCK_in to CCD SUB_PD STROB/Vgate ADC_in BIAS 47/6 CCD signal input Master mode Pin 57(Test1 = Hi) 3.0V 47/6 to V.Baff XSUB SUB_SW/ADCK_in to CCD SUB_PD STROB/Vgate...
  • Page 28 HD49335NP/HNP CDS single operating mode Pin 56(Test2 = Low) Pin 57 is "Don't care" in this mode. 3.0V 47/6 ADC_in CCD signal input Serial data when CDS single operation mode are following resister specifications. (Latch timing specification is same as normal mode) INT1 SDATA D00 D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15...

  • Page 29: Package Dimensions

    HD49335NP/HNP Package Dimensions 9.00 ± 0.1 8.80 C0.50 Index 0.65 0.50 0.05 S 0.40 ± 0.1 Rev.1.0, Feb.12.2004, page 29 of 29 Part A 0.40 ± 0.1 0.20 ± 0.05 Package Code JEDEC Enlargement of Part A JEITA Mass (reference value) Unit: mm 0.05 M S A-B C...
  • Page 30 Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party.

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