C Bus Control Register 2 (Iccr2); Table 15.2 Transfer Rate - Renesas H8/36912 Series User Manual

Table 15.2 Transfer Rate

Bit 3 Bit 2
CKS3 CKS2
0 0
1
1 0
1
2
15.3.2 I

C Bus Control Register 2 (ICCR2)

ICCR2 issues start/stop conditions, manipulates the SDA pin, monitors the SCL pin, and controls
reset in the control part of the I
Bit Bit Name
7 BBSY
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Bit 1 Bit 0
Clock
CKS1 CKS0
φ/28
0 0
φ/40
1
φ/48
1 0
φ/64
1
φ/80
0 0
φ/100
1
φ/112
1 0
φ/128
1
φ/56
0 0
φ/80
1
φ/96
1 0
φ/128
1
φ/160
0 0
φ/200
1
φ/224
1 0
φ/256
1
2
C bus interface 2.
Initial Value R/W Description
0 R/W Bus Busy
This bit enables to confirm whether the I
or released and to issue start/stop conditions in master
mode. With the clocked synchronous serial format, this bit
has no meaning. With the I
when the SDA level changes from high to low under the
condition of SCL = high, assuming that the start condition
has been issued. This bit is cleared to 0 when the SDA level
changes from low to high under the condition of SCL = high,
assuming that the stop condition has been issued. Write 1 to
BBSY and 0 to SCP to issue a start condition. Follow this
procedure when also re-transmitting a start condition. Write 0
in BBSY and 0 in SCP to issue a stop condition. To issue
start/stop conditions, use the MOV instruction.
Transfer Rate
φ φ φ φ = 5 MHz φ φ φ φ = 8 MHz
179 kHz 286 kHz
125 kHz 200 kHz
104 kHz 167 kHz
78.1 kHz 125 kHz
62.5 kHz 100 kHz
50.0 kHz 80.0 kHz
44.6 kHz 71.4 kHz
39.1 kHz 62.5 kHz
89.3 kHz 143 kHz
62.5 kHz 100 kHz
52.1 kHz 83.3 kHz
39.1 kHz 62.5 kHz
31.3 kHz 50.0 kHz
25.0 kHz 40.0 kHz
22.3 kHz 35.7 kHz
19.5 kHz 31.3 kHz
2
C bus format, this bit is set to 1
Rev. 1.00, 11/03, page 229 of 376
φ φ φ φ = 10 MHz
357 kHz
250 kHz
208 kHz
156 kHz
125 kHz
100 kHz
89.3 kHz
78.1 kHz
179 kHz
125 kHz
104 kHz
78.1 kHz
62.5 kHz
50.0 kHz
44.6 kHz
39.1 kHz
2
C bus is occupied