C Bus Control Register 2 (Iccr2) - Renesas H8 Series Hardware Manual

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15.3.2 I

C Bus Control Register 2 (ICCR2)

ICCR2 issues start/stop conditions, manipulates the SDA pin, monitors the SCL pin, and controls
reset in the control part of the I
Bit Bit Name Initial Value R/W Description
7 BBSY 0
6 SCP 1
5 SDAO 1
4 SDAOP 1
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C bus interface 2.
R/W Bus Busy
This bit enables to confirm whether the I
released and to issue start/stop conditions in master mode.
With the clocked synchronous serial format, this bit has no
meaning. With the I
SDA level changes from high to low under the condition of
SCL = high, assuming that the start condition has been
issued. This bit is cleared to 0 when the SDA level changes
from low to high under the condition of SCL = high, assuming
that the stop condition has been issued. Write 1 to BBSY and
0 to SCP to issue a start condition. Follow this procedure
when also re-transmitting a start condition. Write 0 in BBSY
and 0 in SCP to issue a stop condition. To issue start/stop
conditions, use the MOV instruction.
R/W Start/Stop Issue Condition Disable
The SCP bit controls the issue of start/stop conditions in
master mode.
To issue a start condition, write 1 in BBSY and 0 in SCP. A
retransmit start condition is issued in the same way. To issue
a stop condition, write 0 in BBSY and 0 in SCP. This bit is
always read as 1. If 1 is written, the data is not stored.
R/W SDA Output Value Control
This bit is used with SDAOP when modifying output level of
SDA. This bit should not be manipulated during transfer.
0: When reading, SDA pin outputs low.
When writing, SDA pin is changed to output low.
1: When reading, SDA pin outputs high.
When writing, SDA pin is changed to output Hi-Z (outputs
high by external pull-up resistance).
R/W SDAO Write Protect
This bit controls change of output level of the SDA pin by
modifying the SDAO bit. To change the output level, clear
SDAO and SDAOP to 0 or set SDAO to 1 and clear SDAOP
to 0 by the MOV instruction. This bit is always read as 1.
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Section 15 I
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2
C bus format, this bit is set to 1 when the
Rev. 3.00 Sep. 14, 2006 Page 245 of 408
C Bus Interface 2 (IIC2)
C bus is occupied or
REJ09B0105-0300