Bus Arbitration Protocol - Analog Devices ADSP-2106x SHARC User Manual

7 Multiprocessing
The ID pins provide a unique identity for each ADSP-2106x in a
2-0
multiprocessing system. The first ADSP-2106x should be assigned
ID=001, the second should be assigned ID=010, and so on. One of the
ADSP-2106xs must be assigned ID=001 in order for the bus
synchronization scheme to function properly. This processor also holds
the external bus control lines stable during reset.
When the ID inputs of an ADSP-2106x are equal to 001, 010, 011, 100,
2-0
101, or 110, it configures itself for a multiprocessor system and maps its
internal memory and IOP registers into the multiprocessor memory
space. ID=000 configures the ADSP-2106x for a single-processor
system. ID=111 is reserved and should not be used.
An ADSP-2106x in a multiprocessor system can determine which
processor is the current bus master, by reading the CRBM(2:0) bits of
the SYSTAT register. These bits give the value of the ID inputs of the
2-0
current bus master.
Conditional instructions can be written that depend upon whether the
ADSP-2106x is the current bus master in a multiprocessor system. The
assembly language mnemonic for this condition code is BM, and its
complement is NBM (not bus master). The BM condition indicates
whether the ADSP-2106x is the current bus master. For a complete list
of condition codes, see "Conditional Instruction Execution" in the
Program Sequencer chapter of this manual. To enable the use of the bus
master condition, bits 17 and 18 of the MODE1 register must both be
zeros; otherwise the condition is always evaluated as false.
7.3.1

Bus Arbitration Protocol

BR1 BR6
The – pins are connected between each ADSP-2106x in a
BR
multiprocessing system, with the number of x lines used equal to
the number of ADSP-2106xs in the system. Each processor drives the
BR
x pin corresponding to its ID inputs and monitors all others. If
BR
2-0
less than six ADSP-2106xs are used in the system, the unused x pins
should be tied high.
When one of the slave ADSP-2106xs needs to become bus master, it
BR
automatically initiates the bus arbitration process by asserting its x
line at the beginning of the cycle. Later in the same cycle it samples the
BR
value of the other x lines.
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