Samsung S3C6400X User Manual page 1161

S3C6400X RISC MICROPROCESSOR
HCLK
tRAD
Xm0ADDR
Xm0CSn[x]
Tacs
Xm0OEn
Xm0DQM[n]
Xm0WAITn
(R)
Xm0DATA
(R)
Xm0WEn
Xm0WAITn
(W)
Xm0DATA
(W)
(Tacs = 0, Tcos = 0, Tacc = 2, Tcoh = 0, Tcah = 0, PMC = 0, ST = 0, DW = 16-bit)
tRCD
tROD
Tcos
tRBED
tRWD
Tcos
tWS
tRDD
Figure 41-7. ROM/SRAM Timing
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
ADDRESS
Tacc
Sampling
nWAIT
3ns
tRDS
DATA
tWH
DATA
ELECTRICAL DATA
tRAD
tRCD
Tcah
tROD
Tcoh
tRBED
tRDH
tRWD
Tcoh
tRDD
41-13