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S3C6400X RISC MICROPROCESSOR
Xm#SCLK
Xm#CKE
'1'
Xm#ADDR
Xm0AP/
Xm1ADDR[10]
tSCSD
Xm#CSnx
Xm#RASn
Xm#CASn
Xm#DQM[n]
Xm0WEndmc/
Xm1WEn
Xm#DATA
Figure 41-12. SDRAM MRS Timing and Auto Refresh Timing (Trp = 2, Trc = 4)
Note : Before executing auto/self refreshing command, all banks must be in idle state.
tSAD
ADDR
ADDR
tSAD
tSCSD
tSRD
tSRD
tSCD
'1'
tSWD
tSWD
tSWD
tSWD
'HiZ'
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
tSAD
ADDR
tSAD
tSCSD
tSCSD
tSRD
tSRD
tSCD
tSWD
tSWD
ELECTRICAL DATA
41-23
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