Samsung S3C6400X User Manual page 1123

IRDA
IRDA LINE STATUS REGISTER(IRDA_LSR)
Register Address
IrDA _LSR 0x7F00_7014
IrDA_LSR
Tx empty
Reserved
Received last byte from
Rx FIFO
Frame length error
PHY error
CRC error
Reserved
Rx FIFO empty
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
38-16
Specifications and information herein are subject to change without notice.
R/W
R
Bit
[7] Transmitter empty. This bit is set to '1' when TX FIFO is
empty and the transmitter front-end is idle.
[6]
[5] Last byte received from RX FIFO. It is set to a '1' when the
microcontroller reads the last byte of a frame from the RX
FIFO and cleared when the MCU reads the IrDA_LSR
[4] Frame length error. It is set to '1' when a frame exceeding
the maximum frame length predefined by IrDA_RXFLL
and IrDA_RXFLH register is received. This bit is cleared
when the microcontroller reads the IrDA_LSR register.
When this error is detected, current frame reception is
terminated. Data receiving is stopped until the next BOF is
detected. Bit 4 is cleared to '0' when the IrDA_LSR
register is read by the microcontroller.
[3] PHY error. In FIR mode, It is set to a '1' when an illegal
4PPM symbol is received. In IrDA_MIR mode, if an abort
pattern (more than 7 consecutive '1's) is received during
reception, this bit is set to '1'. It is cleared when
microcontroller reads the LSR register.
[2] CRC error. Bit 2 is set to '1' when a bad IrDA_CRC is
detected on data receive. It is cleared to '0' when
microcontroller reads the LSR register.
[1]
[0] RX FIFO empty. It indicates that the RX FIFO is empty.
When the state of RX FIFO turns into empty, it is set to '1'.
When the RX FIFO is not empty, it is set to '0'.
S3C6400X RISC MICROPROCESSOR
Description
IrDA Line Status Register
Description
Reserved
register.
Reserved
Reset Value
0x83
Initial State
1
0
0
0
0
0
1
1