Samsung S3C6400X User Manual page 1159

S3C6400X RISC MICROPROCESSOR
EXTCLK
XTIpll
Clock
Disable
VCO
Output
FCLK
Several slow clock cycles (XTIpll or EXTCLK)
Sleep mode is initiated.
Figure 41-6. Sleep Mode Return Oscillation Setting Timing
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
ELECTRICAL DATA
Wake up from sleep mode
tOSC2
41-11