Table of Contents
Advertisement
IRDA
SPECIAL FUNCTION REGISTERS
IRDA CONTROL REGISTER(IRDA_CNT)
Register
Address
IrDA _CNT 0x7F00_7000
IrDA _CNT
TX enable
RX enable
Core loop
MIR half mode
Send IR pulse
Reserved
Frame abort
SD/BW
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
38-12
Specifications and information herein are subject to change without notice.
R/W
R/W
Bit
[7]
TX enabled. Bit 7 must be set to '1' to enable data
transmission in MIR/FIR Ir modes.
[6]
RX enabled. Bit 6 must be set to '1' to enable data receive
[5]
Core loop for software debugging. The IRRX port
connects directly to the IRTX internally.
[4]
MIR half mode. When bit 4 is set to a '1', the operating
speed in the MIR mode changes from 1.152 Mbps to
[3]
Send 1.6-us IR pulse. When the IrDA_MDR[3] bit equals
to a '1' and the CPU writes a '1' to this bit, the transmitting
interface device sends a 1.6-us IR pulse at the end of the
frame. Bit 3 is cleared automatically by the transmitting
interface device at the end of 1.6-us IR pulse data
[2]
[1]
Frame abort. The CPU can intentionally abort data
transmission of a frame by writing a '1' to bit 1. Neither the
end flag nor the CRC bits are appended to the frame. The
receiver will find the frame with the abort pattern in the
MIR mode and a PHY-error in the FIR mode. The CPU
must reset the TX FIFO and reset this bit by writing a '0' to
bit '1' before next frame can be transmitted.
[0]
This signal controls IrDA_SDBW output signal.
It is used for controlling mode (shutdown, band width) of
S3C6400X RISC MICROPROCESSOR
Description
IrDA Control Register
Description
in all MIR/FIR Ir modes.
0.576 Mbps.
transmission.
Reserved
IrDA transceiver.
Reset Value
0x00
Initial State
0
0
0
0
0
0
0
0
Advertisement
Table of Contents
