Samsung S3C6400X User Manual page 1174

ELECTRICAL DATA
Table 41-13. TFT LCD Controller Module Signal Timing Constants
(VDDINT= 1.0V± 0.05V, TA = -40 to 85°C, VDDLCD = 3.3V ± 0.3V, 2.5V ± 0.25V, 1.8V ± 0.15V)
Parameter
VCLK pulse width
VCLK pulse width high
VCLK pulse width low
Vertical sync pulse width
Vertical back porch delay
Vertical front porch dealy
Hsync setup to VCLK falling edge
VDEN set up to VCLK falling edge
VDEN hold from VCLK falling edge
VD setup to VCLK falling edge
VD hold from VCLK falling edge
VSYNC setup to HSYNC falling edge
VSYNC hold from HSYNC falling edge
NOTES:
1. VCLK period
2. HSYNC period
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
41-26
Specifications and information herein are subject to change without notice.
Symbol Min
Tvclk 18
Tvclkh 0.3
Tvclkl 0.3
Tvspw VSPW + 1
Tvbpd VBPD+1
Tvfpd VFPD+1
Tl2csetup 0.3
Tde2csetup 0.3
Tde2chold 0.3
Tvd2csetup 0.3
Tvd2chold 0.3
Tf2hsetup HSPW + 1
Tf2hhold HBPD + HFPD +
HOZVAL + 3
S3C6400X
RISC MICROPROCESSOR
Typ Max
200 –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
Units
ns
Pvclk(1)
Pvclk
Phclk(2)
Phclk
Phclk
Pvclk
Pvclk
Pvclk
Pvclk
Pvclk
Pvclk
Pvclk