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ELECTRICAL DATA
(VDDINT= 1.0V± 0.05V, TA = -40 to 85°C, VDDSYS = 3.3V ± 0.3V, 2.5V ± 0.25V, 1.8V ± 0.15V)
Parameter
VDDpadIO to VDDALIVE
VDDALIVE to VDDINT/VDDARM
VDDARM to PWR_EN(PWRRGTON)
VDDLOGIC/VDDARM to Oscillator stabilization
Oscillator stabilization to nRESET & nTRST high
External clock input high level pulse width
External clock to HCLK (without PLL)
HCLK (internal) to CLKOUT
HCLK (internal) to SCLK
Reset assert time after clock stabilization
PLL Lock Time
Sleep mode return oscillation setting time.
The interval before CPU runs after nRESET is
released.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
41-12
Specifications and information herein are subject to change without notice.
Table 41-7. Clock Timing Constants
Symbol
tOA
tAI
tAE
tOSC
tOR
t
EXTHIGH
t
EX2HC
t
HC2CK
t
HC2SCLK
t
RESW
t
PLL
t
(2)
OSC2
t
RST2RUN
S3C6400X
RISC MICROPROCESSOR
Min
Typ
Max
0
1
1
10
10
1
20
-
5
10
4
10
2
8
4
-
300
-
4
16
2
2
5
-
Unit
ms
us
ns
cycle
us
ns
ns
ns
ns
XTIpll or
EXTCLK
us
XTIpll or
EXTCLK
XTIpll or
EXTCLK
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