Samsung S3C6400X User Manual page 1124

S3C6400X RISC MICROPROCESSOR
IRDA FIFO CONTROL REGISTER(IRDA_FCR)
Register Address
IrDA _FCR 0x7F00_7018
IrDA _FCR
Rx FIFO Trigger level
select
FIFO size select
TX FIFO Clear
Notification
RX FIFO CLEAR
NOTIFICATION
Tx FIFO reset
Rx FIFO reset
FIFO enable
R/W
R/W
Bit
[7:6] Receiver FIFO triggers level selection.
[5] Must set to '1', to use 64 bytes TX and RX FIFO.
[4] This bit will be activated when the FIFO clear is over. This
bit is cleared by the CPU reads this register.
[3] This bit will be activated when the FIFO clear is over. This
bit is cleared by the CPU reads this register.
[2] TX FIFO reset. When set to '1', bit 2 clears all bytes in the
transmitter FIFO and reset its counter to '0'. A '1' written to
[1] RX FIFO reset. When set to '1', bit 1 clears all bytes in the
receiver FIFO and reset its counter to '0'. A '1' written to
[0] FIFO enabled. When set to '1', bit 0 enables both the
transmitter and receiver FIFOs. Bit 0 must be a '1' when
setting other IrDA_FCR bits. Changing bit 0 clears the
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
IrDA FIFO Control Register
Description
Bit 7 Bit 6 64-byte RX FIFO
0 0 01
0 1 16
1 0 32
1 1 56
bit 2 is self-clearing.
bit 1 is self clearing.
FIFO.
IRDA
Reset Value
0x00
Initial State
00
0
0
0
0
0
0
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